Final report WIP

docs/final_report/1-abstract.tex

@@ -1 +1,3 @@
-% !TeX root = index.tex
+% !TeX root = index.tex
+
+\colorbox{yellow}{To be added}

docs/final_report/3-objectives.tex

@@ -13,7 +13,7 @@ of the department's educational mandate.
 \fi
 
 
-This project can be classified as Design and Construction which explores alternative designs of processor architecture and microarchitecture. :
+This project can be classified as Design and Construction type, which explores alternative designs of processor architecture and microarchitecture. Main goals are:
 \begin{enumerate}
 	\item Study and explore computer architectures, SystemVerilog and assembly languages. 
 	\item Compare how well OISC \texttt{MOVE} architecture would perform in low performance microcontroller application comparing to equivalent and most commonly used RISC architecture.
@@ -21,13 +21,14 @@ This project can be classified as Design and Construction which explores alterna
 \end{enumerate}
 
 
+
 \subsection{RISC Processor}
 As this is aimed for low power and performance applications it will be 8bit word processor with four general purpose registers, structure is similar to MIPS.
 RISC architecture will be mainly based on MIPS architecture explained in \autocite{harris_harris_2013}, except it this RISC processor would have 8bit databus and would have multiple optimisations related to 8bit limits. Some minimalistic ideas was also from \autocite{gilreath_laplante_2003}.
 
 
 \subsection{OISC Processor}
-There are number of different implementations that uses only single instruction. OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with short instruction word and SISO configuration.  The main theory for building OISC architecture will be based on \autocite{gilreath_laplante_2003}.
+OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with short instruction word and SISO configuration.  The main theory for building OISC architecture will be based on \autocite{gilreath_laplante_2003}.
 
 \subsection{Design Criteria}
 In order for fair comparison between both architectures, a common design criteria:

docs/final_report/6-results.tex

@@ -66,6 +66,11 @@ Much higher logic components in RISC can be also explained more complicated regi
 
 \subsection{Benchmark Programs}
 
+\colorbox{yellow}{\parbox{\columnwidth}{Description of each function in benchmark to be added.}}
+
+\subsubsection{Performance}
+\colorbox{yellow}{\parbox{\columnwidth}{Data of benchmark functions timings to be added.}}
+
 \subsubsection{Instruction composition}
 This test is performed to investigate instruction composition of each function to see how similar it is between RISC and OISC processors. 
 \begin{description}
@@ -146,10 +151,10 @@ This test is performed to investigate instruction composition of each function t
 	\label{tab:instr_groups_oisc_src}
 \end{blockpage}
 
-Each function was ran on simulated processor, program counter and instruction been recorded into file at every cycle. File recording was done with SytemVerilog test bench, it started recording when program counter matched \texttt{.start} location and stopped when it matched \texttt{.done} location. Code shown in listings \ref{list:asm_risc_test} and \ref{list:asm_oisc_test} enabled both location to be static, not depending on test function executed.
+Each function was ran on simulated processor, program counter and instruction been recorded into file at every cycle. File recording was done with SytemVerilog test bench, it started recording when program counter matched \texttt{.start} location and stopped when it matched \texttt{.done} location. Code shown in listings \ref{asmrisctest} and \ref{asm_oisc_test} enabled both location to be static, not depending on test function executed.
 
 \begin{blockpage}
-	\begin{lstlisting}[frame=single, caption={RISC assembly frame for executring tests}, emph={setup,start,done} label=list:asm_risc_test]
+	\begin{lstlisting}[frame=single, caption={RISC assembly frame for executring tests}, emph={setup,start,done} label=asmrisctest]
 	setup:
 	JUMP .start
 	.done:
@@ -162,7 +167,7 @@ Each function was ran on simulated processor, program counter and instruction be
 \end{blockpage}
 
 \begin{blockpage}
-	\begin{lstlisting}[frame=single, caption={OISC assembly frame for executring tests}, emph={setup,start,done} label={list:asm_oisc_test}]
+	\begin{lstlisting}[frame=single, caption={OISC assembly frame for executring tests}, emph={setup,start,done} label=asm_oisc_test]
 	setup:
 	BR1 .start @1
 	BR0 .start @0
@@ -199,5 +204,6 @@ Figure \ref{fig:program_size} represents effective program size for each test fu
 \end{colfigure}
 
 \subsection{Maximum clock frequency}
+\colorbox{yellow}{Description to be added.}
+
 
-\subsection{}

docs/final_report/7-conclusion.tex

@@ -8,3 +8,5 @@ The final chapter is short and sweet, to the point:
  * Start with the specifics and end with the general.
  * Summarise key result; mention limitations, note anything unexpected.
 \fi
+
+\colorbox{yellow}{Description to be added.}

docs/final_report/index.tex

@@ -112,8 +112,12 @@
 	\end{titlepage}
 	
 	\pagebreak
-	\section{Abstract}\label{sec:abstract}
+	\section*{Abstract}\label{sec:abstract}
 	\input{1-abstract.tex}
+	\vspace*{10cm}
+	\tableofcontents
+	\vfill\null\pagebreak
+	
 	
 	\section{Introduction}\label{sec:introduction}
 	\input{2-introduction.tex}

docs/final_report/index.toc

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+\contentsline {section}{\numberline {1}Introduction}{2}{section.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {1.1}Aims and Objectives}{2}{subsection.1.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {1.2}Supporting Theory}{2}{subsection.1.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {1.3}Project contents}{3}{subsection.1.3}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {section}{\numberline {2}Goals and Objectives}{4}{section.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {2.1}RISC Processor}{4}{subsection.2.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {2.2}OISC Processor}{4}{subsection.2.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {2.3}Design Criteria}{4}{subsection.2.3}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {2.4}Benchmark}{4}{subsection.2.4}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {section}{\numberline {3}Theory and Analytical Bases}{4}{section.3}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {3.1}RISC Processor}{4}{subsection.3.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {3.1.1}Pipelining}{5}{subsubsection.3.1.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {3.1.2}Multiple cores}{6}{subsubsection.3.1.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {3.2}OISC Processor}{6}{subsection.3.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {3.3}Predictions}{6}{subsection.3.3}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {section}{\numberline {4}Technical Method}{7}{section.4}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.1}Machine Code}{7}{subsection.4.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.1.1}RISC}{7}{subsubsection.4.1.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.1.2}OISC}{7}{subsubsection.4.1.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.2}Data flow}{8}{subsection.4.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.2.1}RISC Datapath}{8}{subsubsection.4.2.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.2.2}OISC Datapath}{9}{subsubsection.4.2.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.3}Stack}{9}{subsection.4.3}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.3.1}RISC Stack}{9}{subsubsection.4.3.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.3.2}OISC Stack}{9}{subsubsection.4.3.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.4}Program Counter}{9}{subsection.4.4}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.4.1}RISC PC}{9}{subsubsection.4.4.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.4.2}OISC PC}{9}{subsubsection.4.4.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.5}Arithmetic Logic Unit}{9}{subsection.4.5}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.5.1}OISC ALU}{10}{subsubsection.4.5.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.5.2}RISC ALU}{11}{subsubsection.4.5.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.6}Program Memory}{11}{subsection.4.6}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.6.1}RISC Program Memory}{11}{subsubsection.4.6.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.6.2}OISC Program Memory}{12}{subsubsection.4.6.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.7}Instruction decoding}{12}{subsection.4.7}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.7.1}RISC}{12}{subsubsection.4.7.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.7.2}OISC}{13}{subsubsection.4.7.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.8}Assembly}{13}{subsection.4.8}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.9}System setup}{15}{subsection.4.9}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {section}{\numberline {5}Results and Analysis}{16}{section.5}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {5.1}FPGA logic component composition}{16}{subsection.5.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {5.2}Benchmark Programs}{17}{subsection.5.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {5.2.1}Performance}{17}{subsubsection.5.2.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {5.2.2}Instruction composition}{17}{subsubsection.5.2.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {5.2.3}Program space}{18}{subsubsection.5.2.3}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {5.3}Maximum clock frequency}{19}{subsection.5.3}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {section}{\numberline {6}Conclusion}{19}{section.6}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {section}{\numberline {7}Appendix}{22}{section.7}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {7.1}Processor instruction set tables}{22}{subsection.7.1}% 

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@@ -1728,7 +1734,7 @@ start_ol
 268 2005 592 2378 conicto
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 end_ol grestore 
-gsave 16.142796 30.621559 translate 0.035278 -0.035278 scale
+gsave 15.142796 30.621559 translate 0.035278 -0.035278 scale
 start_ol
 2373 2560 moveto
 2373 2176 lineto
@@ -1750,7 +1756,7 @@ start_ol
 1808 2752 2000 2704 conicto
 2192 2656 2373 2560 conicto
 end_ol grestore 
-gsave 16.494965 30.621559 translate 0.035278 -0.035278 scale
+gsave 15.494965 30.621559 translate 0.035278 -0.035278 scale
 start_ol
 442 3712 moveto
 881 3712 lineto
@@ -1765,10 +1771,10 @@ start_ol
 442 0 lineto
 442 3712 lineto
 end_ol grestore 
-gsave 14.915000 27.821562 translate 0.035278 -0.035278 scale
+gsave 14.692500 27.812250 translate 0.035278 -0.035278 scale
 start_ol
 end_ol grestore 
-gsave 15.137291 27.821562 translate 0.035278 -0.035278 scale
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 start_ol
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@@ -1786,7 +1792,7 @@ start_ol
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 2385 1920 lineto
 end_ol grestore 
-gsave 15.451997 27.821562 translate 0.035278 -0.035278 scale
+gsave 15.229497 27.812250 translate 0.035278 -0.035278 scale
 start_ol
 3064 1388 moveto
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@@ -1811,7 +1817,7 @@ start_ol
 1123 1912 1085 1664 conicto
 2190 1664 lineto
 end_ol grestore 
-gsave 15.886583 27.821562 translate 0.035278 -0.035278 scale
+gsave 15.664083 27.812250 translate 0.035278 -0.035278 scale
 start_ol
 1601 1216 moveto
 1335 1216 1200 1125 conicto
@@ -1844,7 +1850,7 @@ start_ol
 2261 2752 2580 2467 conicto
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 end_ol grestore 
-gsave 16.318672 27.821562 translate 0.035278 -0.035278 scale
+gsave 16.096172 27.812250 translate 0.035278 -0.035278 scale
 start_ol
 2218 2304 moveto
 2218 3712 lineto
@@ -1870,13 +1876,16 @@ start_ol
 1100 969 1243 772 conicto
 1387 576 1658 576 conicto
 end_ol grestore 
-gsave 16.775740 27.821562 translate 0.035278 -0.035278 scale
+gsave 16.553240 27.812250 translate 0.035278 -0.035278 scale
 start_ol
 end_ol grestore 
-gsave 15.412500 28.621562 translate 0.035278 -0.035278 scale
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 start_ol
 end_ol grestore 
-gsave 15.634791 28.621562 translate 0.035278 -0.035278 scale
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+start_ol
+end_ol grestore 
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 start_ol
 1508 3712 moveto
 3197 3712 lineto
@@ -1900,7 +1909,7 @@ start_ol
 515 3296 757 3504 conicto
 1000 3712 1508 3712 conicto
 end_ol grestore 
-gsave 16.109346 28.621562 translate 0.035278 -0.035278 scale
+gsave 15.886846 28.612250 translate 0.035278 -0.035278 scale
 start_ol
 1601 1216 moveto
 1335 1216 1200 1125 conicto
@@ -1933,7 +1942,7 @@ start_ol
 2261 2752 2580 2467 conicto
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 end_ol grestore 
-gsave 16.541436 28.621562 translate 0.035278 -0.035278 scale
+gsave 16.318936 28.612250 translate 0.035278 -0.035278 scale
 start_ol
 2218 448 moveto
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@@ -1967,6 +1976,9 @@ start_ol
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 1924 2112 1658 2112 conicto
 end_ol grestore 
+gsave 16.776003 28.612250 translate 0.035278 -0.035278 scale
+start_ol
+end_ol grestore 
 0.150000 slw
 [] 0 sd
 [] 0 sd