Min 5 年 前
コミット
2fdcc09ef4

ファイルの差分が大きいため隠しています
+ 1 - 1
docs/final_report/1-abstract.tex


ファイルの差分が大きいため隠しています
+ 10 - 10
docs/final_report/2-introduction.tex


+ 2 - 2
docs/final_report/3-objectives.tex

@@ -23,14 +23,14 @@ This project can be classified as a Design and Construction type, which explores
 
 
 \subsection{RISC Processor}
-The RISC architecture will be mainly based on MIPS architecture explained in \autocite{harris_harris_2013}, except it this RISC processor would have 8bit data bus, four general purpose registers and would have multiple optimisations related to 8bit limits. Some of minimalistic design ideas was also from \autocite{gilreath_laplante_2003}.
+The RISC architecture will be mainly based on MIPS architecture explained in \autocite{harris_harris_2013}, except that this RISC processor would have 8bit data bus, four general purpose registers and would have multiple optimisations related to 8bit limits. Some of minimalistic design ideas were also from \autocite{gilreath_laplante_2003}.
 
 
 \subsection{OISC Processor}
 OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with a short instruction word and a SISO configuration. The main theory for building OISC architecture will be based on \autocite{gilreath_laplante_2003}.
 
 \subsection{Design Criteria}
-In order to fairly comparison between both architectures, a common design criteria is set:
+In order to make a fair comparison between both architectures, common design criteria are set:
 \begin{description}
 	\item[$\bullet$] Minimal instruction size
 	\item[$\bullet$] Minimalistic design

ファイルの差分が大きいため隠しています
+ 9 - 9
docs/final_report/4-theory.tex


ファイルの差分が大きいため隠しています
+ 25 - 24
docs/final_report/5-methods.tex


ファイルの差分が大きいため隠しています
+ 15 - 15
docs/final_report/6-results.tex


ファイルの差分が大きいため隠しています
+ 2 - 2
docs/final_report/7-conclusion.tex


BIN
docs/final_report/index.pdf


+ 3 - 3
docs/final_report/index.toc

@@ -24,17 +24,17 @@
 \defcounter {refsection}{0}\relax 
 \contentsline {subsection}{\numberline {4.1}RISC Processor}{4}{subsection.4.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.1.1}Pipelining}{4}{subsubsection.4.1.1}% 
+\contentsline {subsubsection}{\numberline {4.1.1}Pipelining}{5}{subsubsection.4.1.1}% 
 \defcounter {refsection}{0}\relax 
 \contentsline {subsubsection}{\numberline {4.1.2}Multiple cores}{5}{subsubsection.4.1.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.2}OISC Processor}{5}{subsection.4.2}% 
+\contentsline {subsection}{\numberline {4.2}OISC Processor}{6}{subsection.4.2}% 
 \defcounter {refsection}{0}\relax 
 \contentsline {subsubsection}{\numberline {4.2.1}OISC Pipelining}{6}{subsubsection.4.2.1}% 
 \defcounter {refsection}{0}\relax 
 \contentsline {subsection}{\numberline {4.3}Predictions}{6}{subsection.4.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.3.1}Execution time}{6}{subsubsection.4.3.1}% 
+\contentsline {subsubsection}{\numberline {4.3.1}Execution time}{7}{subsubsection.4.3.1}% 
 \defcounter {refsection}{0}\relax 
 \contentsline {subsubsection}{\numberline {4.3.2}Instruction Space}{7}{subsubsection.4.3.2}% 
 \defcounter {refsection}{0}\relax