Restructrure

Updated risc cpu to fit new model, partly implemented com block. Updated
readme. Fixed minor issues that was preveting from verilog to compile.

.gitignore

@@ -18,3 +18,4 @@ rtl_work/
 db/
 output_files/
 incremental_db/
+greybox_tmp/

readme.md

@@ -6,9 +6,11 @@ The aim is to compare similar characteristic RISC and OISC architectures to dete
 * Which processor is easier to implement and expand;
 * Which processor requires less resources to implement;
 * Which processor performs on common benchmark;
-Possible application of both architectures could be use inside of microcontroller or SoC (System on a chip) systems similar to 8bit Atmel AVR or Mirochip PIC microcontrollers, therefore processors must be capable of controlling and communicating with external modules such as UART\footnote{Universal asynchronous receiver-transmitter} and GPIO (General Purpose Input/Output).
 
-## Project Structure
+Possible application of both architectures could be use inside of microcontroller or SoC (System on a chip) systems similar to 8bit Atmel AVR or Mirochip PIC microcontrollers,
+therefore processors must be capable of controlling and communicating with external modules such as UART and GPIO.
+
+## Files Structure
 This project based on Intel Quartus. Hardware is implemented in SystemVerilog.
 Project directories:
 * *src* - All HDL files,
@@ -18,6 +20,45 @@ Project directories:
 * *tools* - Implemented tools like compiler for designed architecture,
 * *memory* - Instructions and machine code,
 * *docs* - All documentation,
+* *quartus* - Quartus generated IP files,
 * *simulation* - ModelSim simulation files.
 
+## Hardware Structure
+The top level has 4 block:
+
+_PLL_ 
+
+Generates various frequences from main 50MHz crystal. Currenty 3 clock are generated:
+* mclk - 1MHz master clock for processor and uart,
+* fclk - 100MHz fast clock for sdram controller,
+* aclk - 32,768kHz auxiliary clock for timers (to be implemented).
+
+
+_SDRAM Block_ 
+
+Includes sdram controller and fifo queues to synchonise data between mclk and fclk. It communicates with processor using 24bit address bus and 16bit data bus. It is up to processor to decide how to efficiantly store data in this memory.
+
+
+_COM Block_
+
+This include all external functions that might be useful for processor, e.g. UART, on board LED and DIP switch control. In future this might include timers or other communication methods. Processor communicates to this block via 8bit address bus and 8bit data bus. The table of addresses to function map will be added in the future. 
+
+_Processor_ 
+
+The processor itself. This desiged to have common interface so RISC and OISC processor and their variations could be simply swapped between without need to rewrite all project.
+
+
+## Implementations
+
+### FPGA
+The hardware is tested on [DE0 Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=593&PartNo=2) FPGA board.
+
+### UART
+Uses [Open Source Documented Verilog UART](https://github.com/freecores/osdvu) library. This is simple 1 file library without any hardware FIFO queues.
+
+Pinout:
+* *RX* - GPIO-0 Pin2 (GPIO_00)
+* *TX* - GPIO-0 Pin4 (GPIO_01)
 
+### SDRAM
+Uses [sdram-controller](https://github.com/stffrdhrn/sdram-controller) library to communicate with sdram chip on DE0 Nano board.

src/blocks/alu.sv

@@ -54,7 +54,7 @@ module alu(
 	logic [1:0] overLSB;
 	logic overFlag;
 	assign overLSB = {a[WORD-1], b[WORD-1], r[WORD-1]};	
-	assign overFlag = overLSB == 3'b110 || overLSB == 3'b001 ? 1 : 0;
+	assign overFlag = (overLSB == 3'b110 || overLSB == 3'b001) ? 1 : 0;
 	assign overflow = sign && arithmeticOp ? overFlag : 0;	
 	
 	// Carry out flag
@@ -62,8 +62,8 @@ module alu(
 
 	always_comb begin
 	case(op)
-		ALU_ADD: {coutF, r} = a + b + cin;
-		ALU_SUB: {coutF, r} = a - b - cin;
+		ALU_ADD: r = a + b + cin;
+		ALU_SUB: r = a - b - cin;
 		ALU_AND: r = a & b;
 		ALU_OR : r = a | b;
 		ALU_XOR: r = a ^ b;

src/project.sv

@@ -1,5 +1,5 @@
 interface processor_port(
-	input clk, rst,	interrupt,
+	input clk, rst,
 
 	// RAM
 	output [23:0]	ram_addr,
@@ -14,7 +14,8 @@ interface processor_port(
 	// COM
 	output [7:0]	com_addr,
 	output [7:0]	com_wr,
-	input  [7:0]	com_rd
+	input  [7:0]	com_rd,
+	input  			com_interrupt
 	);
 
 endinterface
@@ -23,18 +24,20 @@ module com_block(
 	input clk, rst,
 	// Communication to processor
 	input  [7:0]	addr,
-	input  [7:0]	wr_data,
-	output [7:0]	rd_data,
+	input  [7:0]	in_data,
+	output [7:0]	out_data,
+	output 			interrupt,
 
 	// IO
 	output [7:0]	leds,
 	input  [3:0]	switches,
 	output 			uart0_tx,
-	input 			uart0_rx
+	input 			uart0_rx,
+	input 			key1
 );
 
 	/* UART */
-	reg [7:0] uart0_reg;
+	reg [2:0] uart0_reg;
 	reg uart0_transmit;
 	wire [7:0] tx_byte, rx_byte;
 	// Clock divide = 1e6 / (9600 * 4)
@@ -50,68 +53,28 @@ module com_block(
 			.is_transmitting(uart0_reg[2]),
 			.transmit(uart0_transmit)
 	);
-	
-endmodule
-
-interface sdram_ctl_bus;
-	wire [23:0]	ram_addr;
-	wire [15:0] ram_wr_data;
-	wire [15:0] ram_rd_data;
-	wire 		ram_wr_en;
-	wire 		ram_rd_en;
-	wire 		ram_busy;
-	wire 		ram_rd_ready;
-	wire 		ram_rd_ack;
-	
-	modport out(
-		output	ram_addr,
-		output	ram_wr_data,
-		input 	ram_rd_data,
-		output	ram_wr_en,
-		output	ram_rd_en,
-		input	ram_busy,
-		input	ram_rd_ready,
-		input	ram_rd_ack
-	);
-	
-	modport in(
-		input	ram_addr,
-		input	ram_wr_data,
-		output 	ram_rd_data,
-		input	ram_wr_en,
-		input	ram_rd_en,
-		output	ram_busy,
-		output	ram_rd_ready,
-		output	ram_rd_ack
-	);
-endinterface
 
-interface sdram_io_bus(
-	inout  [15:0]	DRAM_DQ,	// Data
-	output [12:0] 	DRAM_ADDR,	// Address
-	output [1:0]	DRAM_DQM,	// Byte Data Mask
-	output    		DRAM_CLK,	// Clock
-	output    		DRAM_CKE,	// Clock Enable
-	output    		DRAM_WE_N,	// Write Enable
-	output    		DRAM_CAS_N, // Column Address Strobe
-	output    		DRAM_RAS_N, // Row Address Strobe
-	output    		DRAM_CS_N,	// Chip Select
-	output [1:0] 	DRAM_BA		// Bank Address
-	);
-//	
-//	modport out (
-//		inout  DRAM_DQ,	
-//		output DRAM_ADDR,	
-//		output DRAM_DQM,	
-//		output DRAM_CLK,	
-//		output DRAM_CKE,	
-//		output DRAM_WE_N,	
-//		output DRAM_CAS_N, 
-//		output DRAM_RAS_N, 
-//		output DRAM_CS_N,	
-//		output DRAM_BA			
-//	);
-endinterface
+	always_ff@(posedge clk) begin
+	//	if(addr == 8'h06) leds <= in_data;
+	//end
+
+	//always_comb begin
+	case(addr)
+			8'h04: out_data <= {5'b0, uart0_reg};
+			8'h05: begin
+				tx_byte <= in_data;
+				uart0_transmit <= 1;
+				out_data <= {5'b0, uart0_reg};
+			end
+			8'h07: out_data <= {4'b0, switches};
+			8'h08: leds <= in_data;
+			default: begin 
+				out_data <= 0;
+				uart0_transmit <= 0;
+			end
+	endcase
+	end
+endmodule
 
 module sdram_block(
 	input mclk, fclk, rst,

src/risc/cpu.sv

@@ -21,6 +21,20 @@ module risc8_cpu(clk, rst, instr, imm, pc, mem_addr, mem_wr_en, mem_wr_data, mem
 	datapath DPATH(clk, rst, rd, rs, imm, alu_op, alu_ex, reg_wr, pc_src, rimm, alu_src, mem_to_reg, pc, mem_addr, mem_rd_data, alu_zero, mem_wr_data, sp_wr, mem_sp);	
 endmodule
 
+module risc8_port(processor_port port);
+	logic clk, rst, mem_wr; 
+	word pc, instr, imm, mem_addr, mem_data, mem_rd_data;
+	
+	assign port.ram_wr_en = mem_wr;
+	assign port.ram_rd_en = ~mem_wr;
+
+	instr_mem #("/home/min/devel/fpga/ucl_project_y3/memory/test.mem") imem0(pc, instr, imm);
+	
+	risc8_cpu cpu0(port.clk, port.rst, instr, imm, pc,
+			port.ram_addr, mem_wr, port.ram_wr_data, port.ram_rd_data);
+
+endmodule
+
 module risc8_cpu_tb;
 	logic clk, rst, mem_wr; 
 	word pc, instr, imm, mem_addr, mem_data, mem_rd_data;	

src/risc/datapath.sv

@@ -34,7 +34,7 @@ module datapath(clk, rst, rd, rs, imm, alu_op, alu_ex, reg_wr, pc_src,
 	word sp_sel;
 	assign sp_sel = (mem_sp) ? sp_next : sp;
 	assign alu_out = (sp_wr) ? sp_sel : alu_result;
-	alu alu0(
+	alu#(.WORD(8)) alu0(
 		.a(alu_srcA),
 		.b(alu_srcB),
 		.op(alu_op),

src/top.sv

@@ -79,13 +79,9 @@ module top(
 
 
 	// Processor
-	wire interrupt;
-	assign interrupt = ~KEY[1];
-
-	processor_port cpu0 (
+	processor_port port0 (
 		.clk(mclk),
 		.rst(rst),
-		.interrupt(interrupt),
 		.ram_addr(ram_addr),
         .ram_wr_data(ram_wr_data),
         .ram_rd_data(ram_rd_data),
@@ -96,45 +92,29 @@ module top(
 		.ram_rd_ack(ram_rd_ack),
 		.com_addr(com0_addr),
 		.com_wr(com0_wr),
-		.com_rd(com0_rd)
+		.com_rd(com0_rd),
+		.com_interrupt(com0_interrupt)
 	);
 
+	risc8_port cpu_port0(port0);
+
 	//Communication block
 	wire [7:0] com0_addr, com0_wr, com0_rd;
+	wire com0_interrupt;
 
 	com_block com0 (
-			.clk(mclk),
-			.rst(rst),
-			.addr(com0_addr),
-			.wr_data(com0_wr),
-			.rd_data(com0_rd),
-			.leds(LED),
-			.switches(SWITCH),
-			.uart0_rx(RX),
-			.uart0_tx(TX)
+		.clk(mclk),
+		.rst(rst),
+		.addr(com0_addr),
+		.in_data(com0_wr),
+		.out_data(com0_rd),
+		.interrupt(com0_interrupt),
+		.leds(LED),
+		.switches(SWITCH),
+		.uart0_rx(RX),
+		.uart0_tx(TX),
+		.key1(~KEY[1])
 	);
-	//assign clk = keys[1];
-	//logic mem_wr;
-	//word pc, instr, imm, mem_addr, mem_data, mem_rd_data;
-	//word ext_rd_data, rd_data;
-	//cpu CPU(clk_slow, rst, instr, imm, pc, mem_addr, mem_wr, mem_data, rd_data);
-	// Instruction memory
-	//instr_mem #("/home/min/devel/fpga/ucl_project_y3/memory/test.mem") IMEM(pc, instr, imm);
-	// System memory
-	//memory RAM(clk, mem_wr, mem_addr, mem_data, mem_rd_data);
-	
-	//assign ext_rd_data = '{0,0,0,0, 0,0,0,is_transmitting};
-	//assign rd_data = (mem_addr == 8'hFF) ? ext_rd_data : mem_rd_data;
-
-	//always_ff@(posedge clk_slow) begin
-	//		if(mem_wr & mem_addr == 8'hFF) begin
-	//			tx_byte <= mem_data;
-	//			transmit <= 1; 
-	//		end
-	//		else begin
-	//			transmit <= 0; 
-	//		end
-	//end
 
 endmodule