Added insystem reset source

UCL_project_y3.qsf

@@ -121,15 +121,12 @@ set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id top_tb
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME top_tb -section_id top_tb
 set_global_assignment -name EDA_TEST_BENCH_FILE src/top.sv -section_id top_tb
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/debug.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/rom.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/project.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/top.sv
 set_global_assignment -name VERILOG_FILE src/blocks/fifo.v
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/sdram_control.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/risc/general.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/risc/datapath.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/risc/cpu.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/risc/controller.sv
 set_global_assignment -name MIF_FILE memory/rom_test.mem
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/clk_div.sv
 set_global_assignment -name VERILOG_FILE src/blocks/uart.v
@@ -139,4 +136,5 @@ set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/memory.sv
 set_global_assignment -name QIP_FILE quartus/pll_clk.qip
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/alu.sv
 set_global_assignment -name QIP_FILE quartus/risc8_rom.qip
-set_global_assignment -name QIP_FILE quartus/m9k_ram_init.qip
+set_global_assignment -name QIP_FILE quartus/m9k_ram_init.qip
+set_global_assignment -name QIP_FILE quartus/m9k_rom_16.qip

scripts/update_oisc8.tcl

@@ -0,0 +1,31 @@
+foreach hardware_name [get_hardware_names] {
+	if { [string match "USB-Blaster*" $hardware_name] } {
+		set usbblaster_name $hardware_name
+	}
+}
+puts "JTAG chain: $usbblaster_name";
+foreach device_name [get_device_names -hardware_name $usbblaster_name] {
+	if { [string match "@1*" $device_name] } {
+		set test_device $device_name
+	}
+}
+puts "Device: $test_device";
+
+
+begin_memory_edit -hardware_name $hardware_name -device_name $device_name
+start_insystem_source_probe -hardware_name $hardware_name -device_name $device_name
+write_source_data -instance_index 0 -value 1 -value_in_hex
+
+puts "Flashing ram...";
+set content [exec cat ./memory/oisc8.data.uhex]
+write_content_to_memory -instance_index 0 -content $content -content_in_hex -start_address 0 -word_count 4096
+
+puts "Flashing rom...";
+set content [exec cat ./memory/oisc8.text.uhex]
+write_content_to_memory -instance_index 1 -content $content -content_in_hex -start_address 0 -word_count 1024
+
+write_source_data -instance_index 0 -value 0 -value_in_hex
+end_insystem_source_probe
+end_memory_edit
+puts "Done";
+

src/blocks/debug.sv

@@ -0,0 +1,74 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+module altsource_probe_top
+#(
+    parameter lpm_type = "altsource_probe",     // required by the coding standard
+    parameter lpm_hint = "UNUSED",              // required by the coding standard 
+
+    parameter sld_auto_instance_index = "YES",  // Yes, if the instance index should be automatically assigned.
+    parameter sld_instance_index = 0,           // unique identifier for the altsource_probe instance.
+    parameter sld_node_info_parameter = 4746752 + sld_instance_index,   // The NODE ID to uniquely identify this node on the hub.  Type ID: 9 Version: 0 Inst: 0 MFG ID 110 -- ***NOTE*** this parameter cannot be called SLD_NODE_INFO or Quartus Standard will think it's an ISSP impl.
+    parameter sld_ir_width = 4,                 
+                                        
+    parameter instance_id = "UNUSED",           // optional name for the instance.
+    parameter probe_width = 1,                  // probe port width
+    parameter source_width= 1,                  // source port width
+    parameter source_initial_value = "0",       // initial source port value
+    parameter enable_metastability = "NO"       // yes to add two register
+)
+(
+    input [probe_width - 1 : 0] probe,       // probe inputs
+    output [source_width - 1 : 0] source,    // source outputs
+    input source_clk,                        // clock of the registers used to metastabilize the source output
+    input tri1 source_ena                    // enable of the registers used to metastabilize the source output
+);
+
+    altsource_probe #(
+        .lpm_type(lpm_type),
+        .lpm_hint(lpm_hint),   
+        .sld_auto_instance_index(sld_auto_instance_index),
+        .sld_instance_index(sld_instance_index),
+        .SLD_NODE_INFO(sld_node_info_parameter),
+        .sld_ir_width(sld_ir_width),                          
+        .instance_id(instance_id),
+        .probe_width(probe_width),
+        .source_width(source_width),
+        .source_initial_value(source_initial_value),
+        .enable_metastability(enable_metastability)
+    )issp_impl
+    (
+        .probe(probe),
+        .source(source),
+        .source_clk(source_clk),
+        .source_ena(source_ena)
+    );
+    
+endmodule
+
+module sys_ss (output wire source);
+	parameter NAME = "";
+
+	altsource_probe_top #(
+		.sld_auto_instance_index ("YES"),
+		.sld_instance_index      (0),
+		.instance_id             (NAME),
+		.probe_width             (0),
+		.source_width            (1),
+		.source_initial_value    ("0"),
+		.enable_metastability    ("NO")
+	) in_system_sources_probes_0 (
+		.source     (source), // sources.source
+		.source_ena (1'b1)    // (terminated)
+	);
+
+endmodule

src/top.sv

@@ -42,14 +42,16 @@ module top(
 	`else
 		initial $display("Assuming this is simulation");
 	`endif
-
-	assign rst = ~KEY[0];
+	
+	wire debug_rst;
+	sys_ss#("RST") sys_ss_rst(debug_rst);
+	assign rst = ~KEY[0] | debug_rst;
 	
 	/* Clocks */
 	wire mclk; // Master clock 		1MHz 		(for cpu)
 	wire fclk; // Fast clock 		100MHz 		(for sdram)
 	wire aclk; // Auxiliary clock 	32,768kHz 	(for timers)
-	
+
 	pll_clk pll_clk0 (
 			.inclk0(CLK50),
 			.areset(0),