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@@ -0,0 +1,31 @@
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+@article{beldianu_ziavras_2014,
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+title={ASIC Design of Shared Vector Accelerators for Multicore Processors},
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+DOI={10.1109/sbac-pad.2014.13},
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+journal={2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing},
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+author={Beldianu, Spiridon F. and Ziavras, Sotirios G.},
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+year={2014}
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+},
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+
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+@article{dharshana_balasubramanian_arun_2016,
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+title={Encrypted computation on a one instruction set architecture},
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+DOI={10.1109/iccpct.2016.7530376},
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+journal={2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)},
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+author={Dharshana, K. S. and Balasubramanian, Kannan and Arun, M.},
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+year={2016}
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+},
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+
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+@article{ong_ang_seng_2010,
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+title={Implementation of (15, 9) Reed Solomon Minimal Instruction Set Computing on FPGA using Handel-C},
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+DOI={10.1109/iccaie.2010.5735103},
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+journal={2010 International Conference on Computer Applications and Industrial Electronics},
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+author={Ong, Jia Jan and Ang, L.-M. and Seng, K. P.},
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+year={2010}
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+},
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+
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+@article{yokota_saso_hara-azumi_2017,
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+title={One-instruction set computer-based multicore processors for energy-efficient streaming data processing},
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+DOI={10.1145/3130265.3130318},
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+journal={Proceedings of the 28th International Symposium on Rapid System Prototyping Shortening the Path from Specification to Prototype - RSP '17},
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+author={Yokota, Minato and Saso, Kaoru and Hara-Azumi, Yuko},
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+year={2017}
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+}
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