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@@ -90,13 +90,34 @@ As $C_{total}$ and $V_{DD}$ are constants, measuring power at different frequenc
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\subsection{Benchmark Programs}
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+A number of and programs have been written to test both processors. These involve simple functions that could be commonly used in 8bit processors:
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-\colorbox{yellow}{\parbox{\columnwidth}{Description of each function in benchmark to be added.}}
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+\begin{description}
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+ \item[$\bullet$ Printing:] Sends data to UART. It includes waiting until UART is available for transmission.
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+ \item[$\bullet$ Printing unsinged integer:] Uses binary-coded decimal algorithm to convert 8 or 16bit binary value to decimal value and print it.
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+ \item[$\bullet$ 16bit multiplication:] Uses simple matrix multiplication.
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+ \item[$\bullet$ 16bit division:] Uses Long division algorithm to divide two 16bit numbers, including reminder.
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+ \item[$\bullet$ 16bit modulus:] Uses "Russian Peasant Multiplication" algorithm to perform Modulo operation with two 16bit numbers.
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+ \item[$\bullet$ Prime number calculator:] Uses Sieve of Atkins algorithm to calculate primer numbers up to from number 5 to $2^{16}$.
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+\end{description}
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\subsubsection{Performance}
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-\colorbox{yellow}{\parbox{\columnwidth}{Data of benchmark functions timings to be added.}}
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+This subsection investigates time and clock cycles to run benchmark programs. Simulation was sued to find a number of cycles required to execute each function.
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+
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+Print 16bit decimal and modulus were executed with different arguments to show the worst and the best case scenarios as algorithms length depend on inputs. This is not the case for 16bit multiplication as this it has no branching.
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+Results are shown in Figure \ref{fig:cycles}. In most cases, OISC requires around 55-67\% more instruction, with some exceptions. These results can be better explained in following subsection \ref{subsec:instr_comp}.
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+
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+\begin{colfigure}
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+ \centering
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+ \includegraphics[width=\linewidth]{../tests/cycles.eps}
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+ \captionof{figure}{Simulated results of cycles that taken to perform function.}
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+ \label{fig:cycles}
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+\end{colfigure}
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+
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-\subsubsection{Instruction composition}
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+\subsubsection{Instruction composition}\label{subsec:instr_comp}
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This test is performed to investigate instruction composition of each function to see how similar it is between RISC and OISC processors.
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\begin{description}
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\item[$\bullet$ MOVE] - All instructions that move data around internal processor registers.
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