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@@ -25,15 +25,15 @@
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\begin{tcolorbox}[title=Introduction]
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\begin{Row}\begin{Cell}{2}
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\textbf{Motivation:}\\
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- RISC (Reduced Instruction Set Computer) architecture is usually chosen over CISC (Complex Instruction Set Computer) due to simplicity and lower power consumption. This project one step further and investigates OISC (One Instruction Set Computer) MOVE variant architecture to determinate if it can achieve even better performance.
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+ RISC (Reduced Instruction Set Computer) architecture is usually chosen over CISC (Complex Instruction Set Computer) due to simplicity and lower power consumption. This project goes one step further and investigates OISC (One Instruction Set Computer) MOVE variant architecture to determinate if it can achieve even better performance.
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\end{Cell}\begin{Cell}{2}
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\textbf{About:}\\
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- The aim of this project design 2 novel RISC and OSIC architectures with following points:
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+ The aim of this project was to design two novel RISC and OSIC architectures with following points:
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\begin{description}
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\item[$\bullet$] Design processors such that could be used for microcontroller application (like 8-bit Atmel AVR)
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\item[$\bullet$] Use same design criteria to make fair comparison
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\item[$\bullet$] Implement processors on FPGA board
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- \item[$\bullet$] Design a assembly compiler and common functions
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+ \item[$\bullet$] Design an assembly compiler and common functions
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\end{description}
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\end{Cell}\begin{Cell}{1}
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\textbf{Decided design criteria:}
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@@ -140,7 +140,7 @@
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\end{tcolorbox}
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\begin{tcolorbox}[detach title,beforeafter skip=26pt]
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\textbf{Machine code}\\
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- OISC instruction are fixed 13bit width, 1 bit to set source as immediate value, 4bits for destination address and 8bit for source or immediate.
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+ OISC instructions are fixed 13bit width, 1 bit to set source as immediate value, 4bits for destination address and 8bit for source or immediate.
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\\
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\begin{gather*}
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\scalebox{0.8}{bit index:}
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@@ -272,7 +272,7 @@
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\begin{tcolorbox}[title=Conclusion]
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\begin{description}
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\item[$\bullet$] Processor achieved similar performance in power consumption and FPGA resources
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- \item[$\bullet$] OISC seem to be \textbf{easier} to implement and expand, easily enabling \textbf{pipelining} with hazard control implemented by software.
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+ \item[$\bullet$] OISC seems to be \textbf{easier} to implement and expand, easily enabling \textbf{pipelining} with hazard control implemented by software.
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\item[$\bullet$] OISC takes more instructions to perform same function.
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\item[$\bullet$] OISC assembly is more difficult to write.
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\item[$\bullet$] Further research is need to investigate benefits of multi-data-bus OISC design.
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