registers.c 5.7 KB

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  1. /*
  2. MSP430 Emulator
  3. Copyright (C) 2020 Rudolf Geosits (rgeosits@live.esu.edu)
  4. "MSP430 Emulator" is free software: you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation, either version 3 of the License, or
  7. (at your option) any later version.
  8. "MSP430 Emulator" is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program. If not, see <https://www.gnu.org/licenses/>.
  14. */
  15. #include "registers.h"
  16. //##########+++ MSP430 Register initialization +++##########
  17. void initialize_msp_registers(Emulator *emu)
  18. {
  19. cpu_reset(emu);
  20. emu->cpu->running = false;
  21. }
  22. void update_register_display (Emulator *emu)
  23. {
  24. Cpu *cpu = emu->cpu;
  25. char thing[50] = "....";
  26. if (emu->cpu->running) {
  27. send_control(emu, UPDATE_ALL_REGS_PACKET, (void *)thing, strlen(thing));
  28. return;
  29. }
  30. sprintf(thing, "%04X", cpu->pc);
  31. send_control(emu, UPDATE_REG_R0_PACKET, (void *)thing, strlen(thing));
  32. sprintf(thing, "%04X", cpu->sp);
  33. send_control(emu, UPDATE_REG_R1_PACKET, (void *)thing, strlen(thing));
  34. sprintf(thing, "%04X", sr_to_value(emu));
  35. send_control(emu, UPDATE_REG_R2_PACKET, (void *)thing, strlen(thing));
  36. sprintf(thing, "%04X",(uint16_t) cpu->cg2);
  37. send_control(emu, UPDATE_REG_R3_PACKET, (void *)thing, strlen(thing));
  38. sprintf(thing, "%04X",(uint16_t) cpu->r4);
  39. send_control(emu, UPDATE_REG_R4_PACKET, (void *)thing, strlen(thing));
  40. sprintf(thing, "%04X",(uint16_t) cpu->r5);
  41. send_control(emu, UPDATE_REG_R5_PACKET, (void *)thing, strlen(thing));
  42. sprintf(thing, "%04X",(uint16_t) cpu->r6);
  43. send_control(emu, UPDATE_REG_R6_PACKET, (void *)thing, strlen(thing));
  44. sprintf(thing, "%04X",(uint16_t) cpu->r7);
  45. send_control(emu, UPDATE_REG_R7_PACKET, (void *)thing, strlen(thing));
  46. sprintf(thing, "%04X",(uint16_t) cpu->r8);
  47. send_control(emu, UPDATE_REG_R8_PACKET, (void *)thing, strlen(thing));
  48. sprintf(thing, "%04X",(uint16_t) cpu->r9);
  49. send_control(emu, UPDATE_REG_R9_PACKET, (void *)thing, strlen(thing));
  50. sprintf(thing, "%04X", (uint16_t)cpu->r10);
  51. send_control(emu, UPDATE_REG_R10_PACKET, (void *)thing, strlen(thing));
  52. sprintf(thing, "%04X", (uint16_t)cpu->r11);
  53. send_control(emu, UPDATE_REG_R11_PACKET, (void *)thing, strlen(thing));
  54. sprintf(thing, "%04X", (uint16_t)cpu->r12);
  55. send_control(emu, UPDATE_REG_R12_PACKET, (void *)thing, strlen(thing));
  56. sprintf(thing, "%04X", (uint16_t)cpu->r13);
  57. send_control(emu, UPDATE_REG_R13_PACKET, (void *)thing, strlen(thing));
  58. sprintf(thing, "%04X", (uint16_t)cpu->r14);
  59. send_control(emu, UPDATE_REG_R14_PACKET, (void *)thing, strlen(thing));
  60. sprintf(thing, "%04X", (uint16_t)cpu->r15);
  61. send_control(emu, UPDATE_REG_R15_PACKET, (void *)thing, strlen(thing));
  62. }
  63. //##########+++ Set SR struct Value +++##########
  64. void set_sr_value (Emulator *emu, uint16_t value)
  65. {
  66. Cpu *cpu = emu->cpu;
  67. // reset SR to set it properly...
  68. memset(&cpu->sr, 0, sizeof(Status_reg));
  69. //memcpy(&cpu->sr, &value, 16);
  70. if (value & 0x8000) cpu->sr.reserved |= 0x8000;
  71. if (value & 0x4000) cpu->sr.reserved |= 0x4000;
  72. if (value & 0x2000) cpu->sr.reserved |= 0x2000;
  73. if (value & 0x1000) cpu->sr.reserved |= 0x1000;
  74. if (value & 0x0800) cpu->sr.reserved |= 0x0800;
  75. if (value & 0x0400) cpu->sr.reserved |= 0x0400;
  76. if (value & 0x0200) cpu->sr.reserved |= 0x0200;
  77. cpu->sr.overflow = (value & 0x0100) ? 1 : 0;
  78. cpu->sr.SCG1 = (value & 0x0080) ? 1 : 0;
  79. cpu->sr.SCG0 = (value & 0x0040) ? 1 : 0;
  80. cpu->sr.OSCOFF = (value & 0x0020) ? 1 : 0;
  81. cpu->sr.CPUOFF = (value & 0x0010) ? 1 : 0;
  82. cpu->sr.GIE = (value & 0x0008) ? 1 : 0;
  83. cpu->sr.negative = (value & 0x0004) ? 1 : 0;
  84. cpu->sr.zero = (value & 0x0002) ? 1 : 0;
  85. cpu->sr.carry = (value & 0x0001) ? 1 : 0;
  86. }
  87. //##########+++ Return value from SR struct +++##########
  88. uint16_t sr_to_value(Emulator *emu)
  89. {
  90. Cpu *cpu = emu->cpu;
  91. uint16_t r2 = 0;
  92. // reserved bits not working quite right yet
  93. if (cpu->sr.reserved & 0b1000000) {
  94. r2 |= 0x8000;
  95. }
  96. if (cpu->sr.reserved & 0b0100000) {
  97. r2 |= 0x4000;
  98. }
  99. if (cpu->sr.reserved & 0b0010000) {
  100. r2 |= 0x2000;
  101. }
  102. if (cpu->sr.reserved & 0b0001000) {
  103. r2 |= 0x1000;
  104. }
  105. if (cpu->sr.reserved & 0b0000100) {
  106. r2 |= 0x0800;
  107. }
  108. if (cpu->sr.reserved & 0b0000010) {
  109. r2 |= 0x0400;
  110. }
  111. if (cpu->sr.reserved & 0b0000001) {
  112. r2 |= 0x0200;
  113. }
  114. if (cpu->sr.overflow) {
  115. r2 |= 0x0100;
  116. }
  117. if (cpu->sr.SCG1) {
  118. r2 |= 0x0080;
  119. }
  120. if (cpu->sr.SCG0) {
  121. r2 |= 0x0040;
  122. }
  123. if (cpu->sr.OSCOFF) {
  124. r2 |= 0x0020;
  125. }
  126. if (cpu->sr.CPUOFF) {
  127. r2 |= 0x0010;
  128. }
  129. if (cpu->sr.GIE) {
  130. r2 |= 0x0008;
  131. }
  132. if (cpu->sr.negative) {
  133. r2 |= 0x0004;
  134. }
  135. if (cpu->sr.zero) {
  136. r2 |= 0x0002;
  137. }
  138. if (cpu->sr.carry) {
  139. r2 |= 0x0001;
  140. }
  141. return r2;
  142. }
  143. void cpu_step(Emulator *emu) {
  144. Cpu *cpu = emu->cpu;
  145. if(!cpu->sr.CPUOFF) {
  146. // Instruction Decoder
  147. decode(emu, fetch(emu), EXECUTE);
  148. handle_bcm(emu);
  149. }
  150. // Handle Peripherals
  151. handle_timer_a(emu);
  152. handle_port_1(emu);
  153. handle_usci(emu);
  154. handle_interrupts(emu);
  155. cpu->nsecs += cpu->bcm->cpu_period;
  156. }
  157. void cpu_reset(Emulator *emu) {
  158. Cpu *cpu = emu->cpu;
  159. cpu->pc = 0xC000;
  160. cpu->sp = 0x400;
  161. cpu->nsecs = 0;
  162. memset(&cpu->sr, 0, sizeof(Status_reg));
  163. cpu->cg2 = cpu->r4 = cpu->r5 = cpu->r6 = cpu->r7 =
  164. cpu->r8 = cpu->r9 = cpu->r10 = cpu->r11 = cpu->r12 =
  165. cpu->r13 = cpu->r14 = cpu->r15 = 0;
  166. cpu->interrupt = NULL_VECTOR;
  167. }