usci.c 6.9 KB

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  1. /*
  2. MSP430 Emulator
  3. Copyright (C) 2020 Rudolf Geosits (rgeosits@live.esu.edu)
  4. "MSP430 Emulator" is free software: you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation, either version 3 of the License, or
  7. (at your option) any later version.
  8. "MSP430 Emulator" is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program. If not, see <https://www.gnu.org/licenses/>.
  14. */
  15. #include "usci.h"
  16. /*
  17. int master;
  18. FILE *slave;
  19. int sp;
  20. char c;
  21. void *thrd (void *ctxt)
  22. {
  23. Usci *usci = (Usci *)ctxt;
  24. char buf[64] = {0};
  25. while (true) {
  26. usleep(333);
  27. if ( read(sp, buf, 1) > 0 ) {
  28. while (*usci->IFG2 & RXIFG);
  29. if (*buf == '\n') {
  30. *buf = '\r';
  31. }
  32. if (*buf == '\\') {
  33. // Ah, escape sequence, what will I parse it as?
  34. read(sp, buf, 1);
  35. if (*buf == 'h') {
  36. read(sp, buf, 2);
  37. buf[2] = 0;
  38. *usci->UCA0RXBUF = (uint8_t) strtoul(buf, NULL, 16);
  39. }
  40. }
  41. else {
  42. *usci->UCA0RXBUF = *(uint8_t *) buf;
  43. }
  44. *usci->IFG2 |= RXIFG;
  45. }
  46. }
  47. return NULL;
  48. }
  49. void open_pty (Emulator *emu)
  50. {
  51. Cpu *cpu = emu->cpu;
  52. char slavename[64], buf[64];
  53. struct termios termios_p;
  54. master = posix_openpt(O_RDWR);
  55. grantpt(master);
  56. unlockpt(master);
  57. ptsname_r(master, slavename, sizeof slavename);
  58. snprintf(buf, sizeof buf, "-S%s/%d", strrchr(slavename,'/')+1, master);
  59. // Child (pty)
  60. if( !fork() ) {
  61. char * const args[] = {
  62. "xterm", buf,
  63. NULL
  64. };
  65. setpgid(0, 0);
  66. execvp(args[0], args);
  67. exit(1);
  68. }
  69. // Parent
  70. sp = open(slavename, O_RDWR, O_NONBLOCK);
  71. read(sp, buf, 100);
  72. tcgetattr(sp, &termios_p);
  73. termios_p.c_lflag |= ECHO;
  74. tcsetattr(sp, 0, &termios_p);
  75. pthread_t t;
  76. if( pthread_create(&t, NULL, thrd, (void *)cpu->usci ) ) {
  77. fprintf(stderr, "Error creating thread\n");
  78. }
  79. }
  80. */
  81. const uint32_t VALID_BAUD[] = {
  82. 1200, 2400, 4800, 9600, 19200, 38400, 56000, 115200, 128000, 256000
  83. };
  84. void set_uart_buf(Emulator *emu, uint8_t *buf, int len) {
  85. Usci *usci = emu->cpu->usci;
  86. free(usci->UART_buf_data);
  87. usci->UART_buf_data = malloc(len);
  88. memcpy(usci->UART_buf_data, buf, len);
  89. usci->UART_buf_pnt = 0;
  90. usci->UART_buf_len = len;
  91. }
  92. void handle_usci (Emulator *emu) {
  93. Cpu *cpu = emu->cpu;
  94. Debugger *deb = emu->debugger;
  95. Usci *usci = cpu->usci;
  96. Port_1 *p1 = cpu->p1;
  97. if (!usci->USCI_RESET && (*usci->UCA0CTL1 & 0x01)) {
  98. usci->USCI_RESET = true;
  99. }
  100. else if (usci->USCI_RESET && !(*usci->UCA0CTL1 & 0x01)) {
  101. uint64_t clock = 0;
  102. usci->UART_baud = 0;
  103. usci->USCI_RESET = false;
  104. if((*usci->UCA0CTL1 & 0xc0) == 0x40) { // ACLK
  105. clock = cpu->bcm->aclk_freq;
  106. } else if ((*usci->UCA0CTL1 & 0x80) == 0x80) { // SMCLK
  107. clock = cpu->bcm->smclk_freq;
  108. }
  109. if(clock > 0) {
  110. double baud = clock / *usci->UCA0BR0;
  111. for(int i=0;i < sizeof(VALID_BAUD); i++) {
  112. double diff = ((double)VALID_BAUD[i])/baud;
  113. if(diff < 1.1 && diff > 0.9) { // If error less than +/- 10%
  114. usci->UART_baud = VALID_BAUD[i];
  115. char message[35] = {0};
  116. sprintf(message, "Detected UART Baud Rate: %d\n", usci->UART_baud);
  117. print_console(emu, message);
  118. break;
  119. }
  120. }
  121. }
  122. if(usci->UART_baud == 0) {
  123. print_console(emu, "Invalid UART Baud Rate\n");
  124. }
  125. }
  126. if(usci->UART_baud > 0) {
  127. // Handle signal from RX pin (P1.1)
  128. if (p1->SEL_1 && p1->SEL2_1) {
  129. if((usci->UART_buf_pnt < usci->UART_buf_len) && !(*usci->IFG2 & RXIFG)) {
  130. uint64_t symbol_period = 1000000000/usci->UART_baud;
  131. if(cpu->nsecs >= (usci->UART_buf_sent + symbol_period)) {
  132. *usci->UCA0RXBUF = usci->UART_buf_data[usci->UART_buf_pnt];
  133. *usci->IFG2 |= RXIFG;
  134. usci->UART_buf_pnt++;
  135. usci->UART_buf_sent = cpu->nsecs; // Last time symbol was sent;
  136. if(*usci->IE2 & UCA0RXIE) {
  137. service_interrupt(emu, USCIAB0RX_VECTOR);
  138. }
  139. }
  140. }
  141. }
  142. // Handle sending from TX pin (P1.2)
  143. if (p1->SEL_2 && p1->SEL2_2) {
  144. // UCAxTXIFG
  145. if (*usci->IFG2 & TXIFG) {
  146. uint8_t c = *usci->UCA0TXBUF;
  147. unsigned char str[2];
  148. str[0] = c;
  149. str[1] = 0;
  150. *usci->IFG2 &= ~TXIFG;
  151. if (c & 0xFF) {
  152. if (deb->web_interface) {
  153. print_serial(emu, (char*)&str[0]);
  154. }
  155. *usci->UCA0TXBUF = 0;
  156. }
  157. *usci->IFG2 |= TXIFG;
  158. }
  159. }
  160. }
  161. return;
  162. }
  163. void setup_usci (Emulator *emu)
  164. {
  165. Cpu *cpu = emu->cpu;
  166. Usci *usci = cpu->usci;
  167. static const uint16_t UCA0CTL0_VLOC = 0x60; // Control Register 0
  168. static const uint16_t UCA0CTL1_VLOC = 0x61; // Control Register 1
  169. static const uint16_t UCA0BR0_VLOC = 0x62; // Baud Rate ctl Register 0
  170. static const uint16_t UCA0BR1_VLOC = 0x63; // Baud Rate ctl Register 1
  171. static const uint16_t UCA0MCTL_VLOC = 0x64; // Modulation ctl Register
  172. static const uint16_t UCA0STAT_VLOC = 0x65; // Status Register
  173. static const uint16_t UCA0RXBUF_VLOC = 0x66; // RECV buffer register
  174. static const uint16_t UCA0TXBUF_VLOC = 0x67; // Transmit buffer register
  175. static const uint16_t UCA0ABCTL_VLOC = 0x5D; // Auto-Baud control register
  176. static const uint16_t UCA0IRTCTL_VLOC = 0x5E; // IrDA transmit control reg
  177. static const uint16_t UCA0IRRCTL_VLOC = 0x5F; // IrDA Receive control reg
  178. static const uint16_t IE2_VLOC = 0x01; // SFR interrupt enable register 2
  179. static const uint16_t IFG2_VLOC = 0x03; // SFR interrupt flag register 2
  180. // Set initial values
  181. *(usci->UCA0CTL0 = (uint8_t *) get_addr_ptr(UCA0CTL0_VLOC)) = 0;
  182. *(usci->UCA0CTL1 = (uint8_t *) get_addr_ptr(UCA0CTL1_VLOC)) = 0x01;
  183. *(usci->UCA0BR0 = (uint8_t *) get_addr_ptr(UCA0BR0_VLOC)) = 0;
  184. *(usci->UCA0BR1 = (uint8_t *) get_addr_ptr(UCA0BR1_VLOC)) = 0;
  185. *(usci->UCA0MCTL = (uint8_t *) get_addr_ptr(UCA0MCTL_VLOC)) = 0;
  186. *(usci->UCA0STAT = (uint8_t *) get_addr_ptr(UCA0STAT_VLOC)) = 0;
  187. *(usci->UCA0RXBUF = (uint8_t *) get_addr_ptr(UCA0RXBUF_VLOC)) = 0;
  188. *(usci->UCA0TXBUF = (uint8_t *) get_addr_ptr(UCA0TXBUF_VLOC)) = 0;
  189. *(usci->UCA0ABCTL = (uint8_t *) get_addr_ptr(UCA0ABCTL_VLOC)) = 0;
  190. *(usci->UCA0IRTCTL = (uint8_t *) get_addr_ptr(UCA0IRTCTL_VLOC)) = 0;
  191. *(usci->UCA0IRRCTL = (uint8_t *) get_addr_ptr(UCA0IRRCTL_VLOC)) = 0;
  192. usci->IE2 = (uint8_t *) get_addr_ptr(IE2_VLOC);
  193. usci->IFG2 = (uint8_t *) get_addr_ptr(IFG2_VLOC);
  194. *usci->IFG2 |= TXIFG;
  195. *usci->IFG2 &= ~RXIFG;
  196. usci->UART_buf_data = NULL;
  197. usci->UART_buf_len = 0;
  198. usci->UART_buf_pnt = 0;
  199. usci->UART_buf_sent = 0;
  200. usci->UART_baud = 0;
  201. usci->USCI_RESET = false;
  202. }