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@@ -16,32 +16,19 @@ class Emulator:
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EVENT_SERIAL = 1
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EVENT_SERIAL = 1
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EVENT_GPIO = 2
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EVENT_GPIO = 2
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- P1_0_ON_PACKET = 0x00
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- P1_0_OFF_PACKET = 0x01
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- P1_1_ON_PACKET = 0x02
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- P1_1_OFF_PACKET = 0x03
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- P1_2_ON_PACKET = 0x04
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- P1_2_OFF_PACKET = 0x05
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- P1_3_ON_PACKET = 0x06
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- P1_3_OFF_PACKET = 0x07
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- P1_4_ON_PACKET = 0x08
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- P1_4_OFF_PACKET = 0x09
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- P1_5_ON_PACKET = 0x0A
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- P1_5_OFF_PACKET = 0x0B
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- P1_6_ON_PACKET = 0x0C
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- P1_6_OFF_PACKET = 0x0D
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- P1_7_ON_PACKET = 0x0E
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- P1_7_OFF_PACKET = 0x0F
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-
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REG_NAMES_PORT1 = ['P1OUT', 'P1DIR', 'P1IFG', 'P1IES', 'P1IE', 'P1SEL', 'P1SEL2', 'P1REN', 'P1IN']
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REG_NAMES_PORT1 = ['P1OUT', 'P1DIR', 'P1IFG', 'P1IES', 'P1IE', 'P1SEL', 'P1SEL2', 'P1REN', 'P1IN']
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REG_NAMES_BCM = ['DCOCTL', 'BCSCTL1', 'BCSCTL2', 'BCSCTL3', 'IE1', 'IFG1']
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REG_NAMES_BCM = ['DCOCTL', 'BCSCTL1', 'BCSCTL2', 'BCSCTL3', 'IE1', 'IFG1']
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REG_NAMES_TIMER_A = [
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REG_NAMES_TIMER_A = [
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'TA0CTL', 'TA0R', 'TA0CCTL0', 'TA0CCR0', 'TA0CCTL1', 'TA0CCR1', 'TA0CCTL2', 'TA0CCR2', 'TA0IV',
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'TA0CTL', 'TA0R', 'TA0CCTL0', 'TA0CCR0', 'TA0CCTL1', 'TA0CCR1', 'TA0CCTL2', 'TA0CCR2', 'TA0IV',
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'TA1CTL', 'TA1R', 'TA1CCTL0', 'TA1CCR0', 'TA1CCTL1', 'TA1CCR1', 'TA1CCTL2', 'TA1CCR2', 'TA1IV'
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'TA1CTL', 'TA1R', 'TA1CCTL0', 'TA1CCR0', 'TA1CCTL1', 'TA1CCR1', 'TA1CCTL2', 'TA1CCR2', 'TA1IV'
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]
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]
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- REG_NAMES_USCI = ['UCA0CTL0', 'UCA0CTL1', 'UCA0BR0', 'UCA0BR1', 'UCA0MCTL', 'UCA0STAT',
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- 'UCA0RXBUF', 'UCA0TXBUF', 'UCA0ABCTL', 'UCA0IRTCTL', 'UCA0IRRCTL', 'IFG2'
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- ]
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+ REG_NAMES_USCI = [
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+ 'UCA0CTL0', 'UCA0CTL1', 'UCA0BR0', 'UCA0BR1', 'UCA0MCTL', 'UCA0STAT',
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+ 'UCA0RXBUF', 'UCA0TXBUF', 'UCA0ABCTL', 'UCA0IRTCTL', 'UCA0IRRCTL', 'IFG2'
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+ ]
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+ REG_NAMES_CPU = [
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+ 'PC', 'SP', 'SR', 'CG2', 'R4', 'R5', 'R6', 'R7', 'R8', 'R9', 'R10', 'R11', 'R12', 'R13', 'R14', 'R15'
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+ ]
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def __init__(self, load=None, callback=None):
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def __init__(self, load=None, callback=None):
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# self.process = Popen([path.join(emu_dir, 'MSP430'), str(ws_port)], stdout=PIPE, stderr=PIPE)
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# self.process = Popen([path.join(emu_dir, 'MSP430'), str(ws_port)], stdout=PIPE, stderr=PIPE)
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@@ -89,6 +76,10 @@ class Emulator:
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if self.started:
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if self.started:
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return _msp430emu.get_regs(0x03)
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return _msp430emu.get_regs(0x03)
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+ def get_cpu_regs(self):
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+ if self.started:
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+ return _msp430emu.get_regs(0x04)
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+
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def get_timer_a_regs(self):
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def get_timer_a_regs(self):
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if self.started:
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if self.started:
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return _msp430emu.get_regs(0x07)
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return _msp430emu.get_regs(0x07)
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@@ -200,10 +191,11 @@ class EmulatorWindow(wx.Frame):
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"BCM Registers": (view_menu, 1, wx.NewId(), "Show/Hide Emulator BCM register table", self.ToggleRegisters),
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"BCM Registers": (view_menu, 1, wx.NewId(), "Show/Hide Emulator BCM register table", self.ToggleRegisters),
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"TimerA Registers": (view_menu, 1, wx.NewId(), "Show/Hide Emulator TimerA register table", self.ToggleRegisters),
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"TimerA Registers": (view_menu, 1, wx.NewId(), "Show/Hide Emulator TimerA register table", self.ToggleRegisters),
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"USCI Registers": (view_menu, 1, wx.NewId(), "Show/Hide Emulator USCI register table", self.ToggleRegisters),
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"USCI Registers": (view_menu, 1, wx.NewId(), "Show/Hide Emulator USCI register table", self.ToggleRegisters),
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+ "CPU Registers": (view_menu, 1, wx.NewId(), "Show/Hide Emulator CPU register table", self.ToggleRegisters),
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"Clear serial": (view_menu, 0, wx.NewId(), "Clean text in serial window", lambda e: self.serial.Clear()),
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"Clear serial": (view_menu, 0, wx.NewId(), "Clean text in serial window", lambda e: self.serial.Clear()),
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"Clear console": (view_menu, 0, wx.NewId(), "Clean text in console window", lambda e: self.control.Clear()),
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"Clear console": (view_menu, 0, wx.NewId(), "Clean text in console window", lambda e: self.control.Clear()),
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- "Step\tCtrl+N": (debug_menu, 0, wx.NewId(), "Step single instruction", lambda e: self.emu.send_command("step")),
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+ "Step\tCtrl+N": (debug_menu, 0, wx.NewId(), "Step single instruction", self.OnStep),
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"Registers": (debug_menu, 0, wx.NewId(), "Print registers in console", lambda e: self.emu.send_command("regs")),
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"Registers": (debug_menu, 0, wx.NewId(), "Print registers in console", lambda e: self.emu.send_command("regs")),
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}
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}
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@@ -452,6 +444,10 @@ class EmulatorWindow(wx.Frame):
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self.emu.write_serial(text)
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self.emu.write_serial(text)
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self.serial_input.Clear()
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self.serial_input.Clear()
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+ def OnStep(self, e):
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+ self.emu.send_command("step")
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+ self.registers.update_values()
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+
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def ToggleRegisters(self, e):
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def ToggleRegisters(self, e):
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if e.Id == self.menu_navigation["Port1 Registers"][2]:
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if e.Id == self.menu_navigation["Port1 Registers"][2]:
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panel = self.registers.panel_port1
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panel = self.registers.panel_port1
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@@ -461,6 +457,8 @@ class EmulatorWindow(wx.Frame):
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panel = self.registers.panel_timer_a
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panel = self.registers.panel_timer_a
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elif e.Id == self.menu_navigation["USCI Registers"][2]:
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elif e.Id == self.menu_navigation["USCI Registers"][2]:
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panel = self.registers.panel_usci
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panel = self.registers.panel_usci
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+ elif e.Id == self.menu_navigation["CPU Registers"][2]:
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+ panel = self.registers.panel_cpu
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else:
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else:
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return
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return
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if e.Int == 0:
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if e.Int == 0:
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@@ -480,16 +478,19 @@ class RegisterPanel(wx.Panel):
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self.regs_bcm = {name: None for name in emu.REG_NAMES_BCM + ["MCLK"]}
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self.regs_bcm = {name: None for name in emu.REG_NAMES_BCM + ["MCLK"]}
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self.regs_timer_a = {name: None for name in emu.REG_NAMES_TIMER_A}
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self.regs_timer_a = {name: None for name in emu.REG_NAMES_TIMER_A}
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self.regs_usci = {name: None for name in emu.REG_NAMES_USCI}
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self.regs_usci = {name: None for name in emu.REG_NAMES_USCI}
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+ self.regs_cpu = {name: None for name in emu.REG_NAMES_CPU}
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self.grid_port1 = wx.FlexGridSizer(len(self.regs_port1), 2, 0, 10)
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self.grid_port1 = wx.FlexGridSizer(len(self.regs_port1), 2, 0, 10)
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self.grid_bmc = wx.FlexGridSizer(len(self.regs_bcm), 2, 0, 10)
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self.grid_bmc = wx.FlexGridSizer(len(self.regs_bcm), 2, 0, 10)
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self.grid_timer_a = wx.FlexGridSizer(len(self.regs_timer_a), 2, 0, 10)
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self.grid_timer_a = wx.FlexGridSizer(len(self.regs_timer_a), 2, 0, 10)
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self.grid_usci = wx.FlexGridSizer(len(self.regs_usci), 2, 0, 10)
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self.grid_usci = wx.FlexGridSizer(len(self.regs_usci), 2, 0, 10)
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+ self.grid_cpu = wx.FlexGridSizer(len(self.regs_cpu), 2, 0, 5)
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self.panel_port1 = wx.Panel(self)
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self.panel_port1 = wx.Panel(self)
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self.panel_bmc = wx.Panel(self)
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self.panel_bmc = wx.Panel(self)
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self.panel_timer_a = wx.Panel(self)
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self.panel_timer_a = wx.Panel(self)
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self.panel_usci = wx.Panel(self)
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self.panel_usci = wx.Panel(self)
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+ self.panel_cpu = wx.Panel(self)
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# Stucture map of [panel, grid, regs, emu func]
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# Stucture map of [panel, grid, regs, emu func]
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self.__struc = [
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self.__struc = [
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@@ -497,6 +498,7 @@ class RegisterPanel(wx.Panel):
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(self.panel_bmc, self.grid_bmc, self.regs_bcm, emu.get_bcm_regs),
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(self.panel_bmc, self.grid_bmc, self.regs_bcm, emu.get_bcm_regs),
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(self.panel_timer_a, self.grid_timer_a, self.regs_timer_a, emu.get_timer_a_regs),
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(self.panel_timer_a, self.grid_timer_a, self.regs_timer_a, emu.get_timer_a_regs),
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(self.panel_usci, self.grid_usci, self.regs_usci, emu.get_usci_regs),
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(self.panel_usci, self.grid_usci, self.regs_usci, emu.get_usci_regs),
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+ (self.panel_cpu, self.grid_cpu, self.regs_cpu, emu.get_cpu_regs),
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]
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]
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for panel, grid, regs, _ in self.__struc:
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for panel, grid, regs, _ in self.__struc:
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@@ -515,6 +517,7 @@ class RegisterPanel(wx.Panel):
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vbox.Add(self.panel_bmc, proportion=1, flag=wx.ALL | wx.EXPAND)
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vbox.Add(self.panel_bmc, proportion=1, flag=wx.ALL | wx.EXPAND)
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self.box.Add(vbox, proportion=1, flag=wx.ALL | wx.EXPAND, border=5)
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self.box.Add(vbox, proportion=1, flag=wx.ALL | wx.EXPAND, border=5)
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self.box.Add(self.panel_timer_a, proportion=1, flag=wx.ALL | wx.EXPAND, border=5)
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self.box.Add(self.panel_timer_a, proportion=1, flag=wx.ALL | wx.EXPAND, border=5)
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+ self.box.Add(self.panel_cpu, proportion=1, flag=wx.ALL | wx.EXPAND, border=5)
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self.box.Add(self.panel_usci, proportion=1, flag=wx.ALL | wx.EXPAND, border=5)
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self.box.Add(self.panel_usci, proportion=1, flag=wx.ALL | wx.EXPAND, border=5)
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self.SetSizer(self.box)
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self.SetSizer(self.box)
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self.Center()
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self.Center()
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@@ -526,8 +529,8 @@ class RegisterPanel(wx.Panel):
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values = func()
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values = func()
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if values is None:
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if values is None:
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return None
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return None
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- formatted = [f"{value:08b}" for value in values]
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if panel == self.panel_bmc:
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if panel == self.panel_bmc:
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+ formatted = [f"{value:08b}" for value in values]
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freq = "x"
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freq = "x"
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if values[0] == 96 and values[1] == 135:
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if values[0] == 96 and values[1] == 135:
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freq = "1.03"
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freq = "1.03"
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@@ -540,6 +543,10 @@ class RegisterPanel(wx.Panel):
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elif values[0] == 0b10010101 and values[1] == 0b10001111:
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elif values[0] == 0b10010101 and values[1] == 0b10001111:
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freq = "16.0"
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freq = "16.0"
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formatted.append(freq + " MHz")
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formatted.append(freq + " MHz")
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+ elif panel == self.panel_cpu:
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+ formatted = ["0x%0.4X" % int.from_bytes(values[i:i+2], sys.byteorder) for i in range(0, len(values), 2)]
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+ else:
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+ formatted = [f"{value:08b}" for value in values]
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return formatted
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return formatted
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def update_values(self):
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def update_values(self):
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