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+/******************************************************************************
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+* @file system_msp432p401r.c
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+* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
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+* MSP432P401R
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+* @version 3.231
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+* @date 01/26/18
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+*
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+* @note View configuration instructions embedded in comments
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+*
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+******************************************************************************/
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+//*****************************************************************************
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+//
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+// Copyright (C) 2015 - 2018 Texas Instruments Incorporated - http://www.ti.com/
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+//
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+// Redistribution and use in source and binary forms, with or without
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+// modification, are permitted provided that the following conditions
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+// are met:
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+//
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+// Redistributions of source code must retain the above copyright
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+// notice, this list of conditions and the following disclaimer.
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+//
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+// Redistributions in binary form must reproduce the above copyright
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+// notice, this list of conditions and the following disclaimer in the
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+// documentation and/or other materials provided with the
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+// distribution.
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+//
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+// Neither the name of Texas Instruments Incorporated nor the names of
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+// its contributors may be used to endorse or promote products derived
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+// from this software without specific prior written permission.
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+//
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+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+//
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+//*****************************************************************************
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+
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+#include <stdint.h>
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+#include <ti/devices/msp432p4xx/inc/msp.h>
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+
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+/*--------------------- Configuration Instructions ----------------------------
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+ 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
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+ #define __HALT_WDT 1
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+ 2. Insert your desired CPU frequency in Hz at:
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+ #define __SYSTEM_CLOCK 12000000
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+ 3. If you prefer the DC-DC power regulator (more efficient at higher
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+ frequencies), set the __REGULATOR to 1:
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+ #define __REGULATOR 1
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+ *---------------------------------------------------------------------------*/
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+
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+/*--------------------- Watchdog Timer Configuration ------------------------*/
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+// Halt the Watchdog Timer
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+// <0> Do not halt the WDT
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+// <1> Halt the WDT
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+#define __HALT_WDT 1
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+
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+/*--------------------- CPU Frequency Configuration -------------------------*/
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+// CPU Frequency
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+// <1500000> 1.5 MHz
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+// <3000000> 3 MHz
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+// <12000000> 12 MHz
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+// <24000000> 24 MHz
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+// <48000000> 48 MHz
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+#define __SYSTEM_CLOCK 3000000
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+
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+/*--------------------- Power Regulator Configuration -----------------------*/
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+// Power Regulator Mode
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+// <0> LDO
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+// <1> DC-DC
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+#define __REGULATOR 0
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+
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+/*----------------------------------------------------------------------------
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+ Define clocks, used for SystemCoreClockUpdate()
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+ *---------------------------------------------------------------------------*/
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+#define __VLOCLK 10000
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+#define __MODCLK 24000000
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+#define __LFXT 32768
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+#define __HFXT 48000000
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+
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+/*----------------------------------------------------------------------------
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+ Clock Variable definitions
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+ *---------------------------------------------------------------------------*/
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+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
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+
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+/**
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+ * Update SystemCoreClock variable
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+ *
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+ * @param none
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+ * @return none
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+ *
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+ * @brief Updates the SystemCoreClock with current core Clock
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+ * retrieved from cpu registers.
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+ */
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+void SystemCoreClockUpdate(void)
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+{
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+ uint32_t source = 0, divider = 0, dividerValue = 0, centeredFreq = 0, calVal = 0;
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+ int16_t dcoTune = 0;
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+ float dcoConst = 0.0;
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+
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+ divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
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+ dividerValue = 1 << divider;
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+ source = CS->CTL1 & CS_CTL1_SELM_MASK;
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+
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+ switch(source)
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+ {
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+ case CS_CTL1_SELM__LFXTCLK:
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+ if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
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+ {
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+ // Clear interrupt flag
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+ CS->KEY = CS_KEY_VAL;
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+ CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
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+ CS->KEY = 1;
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+
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+ if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
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+ {
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+ if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
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+ {
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+ SystemCoreClock = (128000 / dividerValue);
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+ }
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+ else
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+ {
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+ SystemCoreClock = (32000 / dividerValue);
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+ }
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+ }
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+ else
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+ {
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+ SystemCoreClock = __LFXT / dividerValue;
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+ }
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+ }
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+ else
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+ {
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+ SystemCoreClock = __LFXT / dividerValue;
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+ }
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+ break;
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+ case CS_CTL1_SELM__VLOCLK:
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+ SystemCoreClock = __VLOCLK / dividerValue;
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+ break;
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+ case CS_CTL1_SELM__REFOCLK:
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+ if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
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+ {
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+ SystemCoreClock = (128000 / dividerValue);
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+ }
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+ else
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+ {
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+ SystemCoreClock = (32000 / dividerValue);
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+ }
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+ break;
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+ case CS_CTL1_SELM__DCOCLK:
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+ dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
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+
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+ switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
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+ {
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+ case CS_CTL0_DCORSEL_0:
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+ centeredFreq = 1500000;
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+ break;
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+ case CS_CTL0_DCORSEL_1:
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+ centeredFreq = 3000000;
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+ break;
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+ case CS_CTL0_DCORSEL_2:
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+ centeredFreq = 6000000;
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+ break;
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+ case CS_CTL0_DCORSEL_3:
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+ centeredFreq = 12000000;
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+ break;
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+ case CS_CTL0_DCORSEL_4:
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+ centeredFreq = 24000000;
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+ break;
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+ case CS_CTL0_DCORSEL_5:
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+ centeredFreq = 48000000;
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+ break;
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+ }
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+
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+ if(dcoTune == 0)
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+ {
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+ SystemCoreClock = centeredFreq;
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+ }
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+ else
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+ {
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+
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+ if(dcoTune & 0x1000)
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+ {
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+ dcoTune = dcoTune | 0xF000;
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+ }
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+
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+ if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
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+ {
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+ dcoConst = *((volatile const float *) &TLV->DCOER_CONSTK_RSEL04);
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+ calVal = TLV->DCOER_FCAL_RSEL04;
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+ }
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+ /* Internal Resistor */
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+ else
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+ {
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+ dcoConst = *((volatile const float *) &TLV->DCOIR_CONSTK_RSEL04);
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+ calVal = TLV->DCOIR_FCAL_RSEL04;
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+ }
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+
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+ SystemCoreClock = (uint32_t) ((centeredFreq)
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+ / (1
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+ - ((dcoConst * dcoTune)
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+ / (8 * (1 + dcoConst * (768 - calVal))))));
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+ }
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+ break;
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+ case CS_CTL1_SELM__MODOSC:
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+ SystemCoreClock = __MODCLK / dividerValue;
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+ break;
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+ case CS_CTL1_SELM__HFXTCLK:
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+ if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
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+ {
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+ // Clear interrupt flag
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+ CS->KEY = CS_KEY_VAL;
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+ CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
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+ CS->KEY = 1;
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+
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+ if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
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+ {
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+ if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
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+ {
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+ SystemCoreClock = (128000 / dividerValue);
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+ }
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+ else
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+ {
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+ SystemCoreClock = (32000 / dividerValue);
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+ }
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+ }
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+ else
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+ {
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+ SystemCoreClock = __HFXT / dividerValue;
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+ }
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+ }
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+ else
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+ {
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+ SystemCoreClock = __HFXT / dividerValue;
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+ }
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+ break;
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+ }
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+}
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+
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+/**
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+ * Initialize the system
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+ *
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+ * @param none
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+ * @return none
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+ *
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+ * @brief Setup the microcontroller system.
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+ *
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+ * Performs the following initialization steps:
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+ * 1. Enables the FPU
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+ * 2. Halts the WDT if requested
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+ * 3. Enables all SRAM banks
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+ * 4. Sets up power regulator and VCORE
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+ * 5. Enable Flash wait states if needed
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+ * 6. Change MCLK to desired frequency
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+ * 7. Enable Flash read buffering
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+ */
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+void SystemInit(void)
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+{
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+ // Enable FPU if used
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+ #if (__FPU_USED == 1) // __FPU_USED is defined in core_cm4.h
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+ SCB->CPACR |= ((3UL << 10 * 2) | // Set CP10 Full Access
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+ (3UL << 11 * 2)); // Set CP11 Full Access
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+ #endif
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+
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+ #if (__HALT_WDT == 1)
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+ WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
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+ #endif
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+
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+ SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
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+
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+ #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
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+ // Default VCORE is LDO VCORE0 so no change necessary
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+
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+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
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+ #if __REGULATOR
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+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
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+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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+ #endif
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+
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+ // No flash wait states necessary
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+
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+ // DCO = 1.5 MHz; MCLK = source
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+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
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+ CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
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+ CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
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+ // Select MCLK as DCO source
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+ CS->KEY = 0;
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+
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+ // Set Flash Bank read buffering
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+ FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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+ FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
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+
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+ #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
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+ // Default VCORE is LDO VCORE0 so no change necessary
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+
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+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
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+ #if __REGULATOR
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+ while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
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+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
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+ while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
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+ #endif
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+
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+ // No flash wait states necessary
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+
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+ // DCO = 3 MHz; MCLK = source
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+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
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+ CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
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+ CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
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+ // Select MCLK as DCO source
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+ CS->KEY = 0;
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+
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+ // Set Flash Bank read buffering
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+ FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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+ FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
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+
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+ #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
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+ // Default VCORE is LDO VCORE0 so no change necessary
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+
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+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
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+ #if __REGULATOR
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+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
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+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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+ #endif
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+
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+ // No flash wait states necessary
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+
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+ // DCO = 12 MHz; MCLK = source
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+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
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+ CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
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+ CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
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+ // Select MCLK as DCO source
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+ CS->KEY = 0;
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+
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+ // Set Flash Bank read buffering
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+ FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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+ FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
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+
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+ #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
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+ // Default VCORE is LDO VCORE0 so no change necessary
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+
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+ // Switches LDO VCORE0 to DCDC VCORE0 if requested
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+ #if __REGULATOR
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+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
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+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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+ #endif
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+
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+ // 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
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+ FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1;
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+ FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1;
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+
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+ // DCO = 24 MHz; MCLK = source
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+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
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+ CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
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+ CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
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+ // Select MCLK as DCO source
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+ CS->KEY = 0;
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+
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+ // Set Flash Bank read buffering
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+ FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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+ FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
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+
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+ #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
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+ // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
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+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
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+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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+
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+ // Switches LDO VCORE1 to DCDC VCORE1 if requested
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+ #if __REGULATOR
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+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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+ PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
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+ while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
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+ #endif
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+
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+ // 1 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
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+ FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1;
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+ FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1;
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+
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+ // DCO = 48 MHz; MCLK = source
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+ CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
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+ CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
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+ CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
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+ // Select MCLK as DCO source
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+ CS->KEY = 0;
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+
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+ // Set Flash Bank read buffering
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+ FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
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+ FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL | (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
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+ #endif
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+
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+}
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+
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+
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