altera_devel/src/fpu16/fpu16.sv

`include "fp_adder.sv"
`include "fp_product.sv"


module fpu16_tb;
	reg reset, clk;
	logic [15:0] input_a, input_b, result_add, result_mult;
	logic [15:0] expected_add, expected_mult;

	fp_adder adder1(.input_a(input_a), .input_b(input_b), .output_z(result_add), .clk(clk), .reset(reset));

	fp_product multiplier1(.input_a(input_a), .input_b(input_b), .output_z(result_mult), .clk(clk), .reset(reset));
	
	initial forever #5 clk = ~clk;
	localparam PIPELINES = 3;

	reg [15:0] test_mem [29:0][3:0];

	initial $readmemh("scripts/fp16_test.hex", test_mem);

	initial begin
        static int num_err = 0;
        static int num_tests = $size(test_mem) * 2;

		clk = 0;
		reset = 1;
		  
		#15;
		reset = 0;

		expected_add = 0;
		expected_mult = 0;

        for (int i=0; i < $size(test_mem)+PIPELINES; i++) begin
			if(i >= PIPELINES) begin
				expected_add = test_mem[i-PIPELINES][2];
				expected_mult = test_mem[i-PIPELINES][3];
			end
            input_a = test_mem[i][0];
            input_b = test_mem[i][1];

            #10;
            if(result_add != expected_add) begin
                if(num_err < 20)
                    $display("FAIL ADD: %H + %H = %H, expected %H", test_mem[i-PIPELINES][0], test_mem[i-PIPELINES][1], result_add, test_mem[i][2]);
                num_err = num_err + 1;
            end

			if(result_mult != expected_mult) begin
                if(num_err < 20)
                    $display("FAIL MULTIPLY: %H x %H = %H, expected %H", test_mem[i-PIPELINES][0], test_mem[i-PIPELINES][1], result_mult, test_mem[i][3]);
                num_err = num_err + 1;
            end

		end
		expected_add = 0;
		expected_mult = 0;
		#50;
        $display("Passed %d of %d tests", num_tests-num_err, num_tests);
        $finish();
	end
endmodule : fpu16_tb