altera_devel/scripts/number_conv.py

import numpy as np
from fpu_test_gen import reverse_endian, dtype_size
import sys


def float2verilog(lines, dtype=np.float32):
    dsize = dtype_size(dtype)
    print("")
    for i, line in enumerate(lines):
        arr = line.replace('[', '').replace(']', '').replace('#', '').replace('/', '').split()
        nums = np.array([float(f.strip(',')) for f in arr if f], dtype=dtype)
        b = nums.tobytes()
        print(f'[{i}] = {{' +
              ', '.join(["'h" + reverse_endian(b[i*dsize:i*dsize+dsize]).hex() for i in range(len(arr))]) +
              '};')


if __name__ == '__main__':
    print("Press Ctrl-D to proceed")
    while True:
        lines = sys.stdin.readlines()
        if len(lines) == 0:
            break
        float2verilog(lines)