altera_devel/Makefile

QUARTUS_ROOT := /opt/intelFPGA/* C:/intelFPGA_lite/*

### Finding quartus dir. If not found, edit QUARTUS_ROOT above
QUARTUS_ROOT_PATH = $(word 1, $(foreach dir, $(QUARTUS_ROOT), $(wildcard $(dir))))
ifeq ($(QUARTUS_ROOT_PATH),)
$(error Failed to find Quartus installation dir, change QUARTUS_ROOT parameter)
endif

### Finding needed binary files
QUARTUS_SH = $(word 1, $(wildcard $(QUARTUS_ROOT_PATH)/quartus/*/quartus_sh))
QUARTUS_MAP = $(word 1, $(wildcard $(QUARTUS_ROOT_PATH)/quartus/*/quartus_map))
MODELSIM_BIN = $(word 1, $(wildcard $(QUARTUS_ROOT_PATH)/modelsim_ase/*/vsim))

### Checking if we have everything we need
ifeq ($(QUARTUS_SH),)
$(error Failed to find QUARTUS_SH)
endif
ifeq ($(QUARTUS_MAP),)
$(error Failed to find QUARTUS_MAP)
endif
ifeq ($(MODELSIM_BIN),)
$(error Failed to find MODELSIM_BIN)
endif

$(info QUARTUS_MAP=$(QUARTUS_MAP))
$(info MODELSIM_BIN=$(MODELSIM_BIN))

### Remaining configurations
PROJECT_NAME = altera_devel
QUARTUS_MACROS = --set VERILOG_MACRO="SYNTHESIS=1"
VSIM_ARGS = -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -voptargs="+acc"


### Optional parameters
tb_file ?=
tb_dir = $(dirname "${testbench_file}")
tb_mod ?=
do_file ?=

### ================================================================
### Commands
### ================================================================

analysis:
	${QUARTUS_MAP} --read_settings_files=on --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} --analysis_and_elaboration

modelsim: analysis
	${QUARTUS_SH} -t "${QUARTUS_ROOT_PATH}/quartus/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "${PROJECT_NAME}" "${PROJECT_NAME}"

modelsim_cli:
	${MODELSIM_BIN} -c

sim:
	cd ./simulation/modelsim && ${MODELSIM_BIN} -c -do "${do_file}"

sim_gui:
	cd ./simulation/modelsim && ${MODELSIM_BIN} -gui -do "${do_file}"

testbench:
	${MODELSIM_BIN} -c -do "vlog -sv +incdir+${tb_dir} {${tb_file}}; vsim -t 1ps ${VSIM_ARGS} ${tb_mod}; run -all"