altera_devel/Makefile

QUARTUS_ROOT := /opt/intelFPGA/* C:/intelFPGA_lite/*

### Finding quartus dir. If not found, edit QUARTUS_ROOT above
QUARTUS_ROOT_PATH = $(word 1, $(foreach dir, $(QUARTUS_ROOT), $(wildcard $(dir))))
ifeq ($(QUARTUS_ROOT_PATH),)
$(error Failed to find Quartus installation dir, change QUARTUS_ROOT parameter)
endif

### Finding needed binary files
QUARTUS_SH = $(word 1, $(wildcard $(QUARTUS_ROOT_PATH)/quartus/*/quartus_sh))
QUARTUS_MAP = $(word 1, $(wildcard $(QUARTUS_ROOT_PATH)/quartus/*/quartus_map))
MODELSIM_BIN = $(word 1, $(wildcard $(QUARTUS_ROOT_PATH)/modelsim_ase/*/vsim))

### Checking if we have everything we need
ifeq ($(QUARTUS_SH),)
$(error Failed to find QUARTUS_SH)
endif
ifeq ($(QUARTUS_MAP),)
$(error Failed to find QUARTUS_MAP)
endif
ifeq ($(MODELSIM_BIN),)
$(error Failed to find MODELSIM_BIN)
endif

$(info QUARTUS_MAP=$(QUARTUS_MAP))
$(info MODELSIM_BIN=$(MODELSIM_BIN))

### Remaining configurations
PROJECT_NAME = altera_devel
QUARTUS_MACROS = --set VERILOG_MACRO="SYNTHESIS=1"
VSIM_ARGS = -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -voptargs="+acc"


### VERILOG SOURCE FILES
## It finds all verilog files in src/*.sv and
## also includes subdirectories that has syntax
## src/{MOD_NAME}/{MOD_NAME}.sv or src/{MOD_NAME}/include.sv
###
VERILOG_SRC=$(foreach SRC,$(sort $(dir $(wildcard ./src/*/*.sv))),$(wildcard $(SRC)$(shell basename $(SRC)).sv $(SRC)include.sv)) $(wildcard ./src/*.sv)
$(info VERILOG_SRC=$(VERILOG_SRC))
SIM_DIR ?= ./simulation/modelsim

### ================================================================
### Commands
### ================================================================

analysis:
	${QUARTUS_MAP} --read_settings_files=on --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} --analysis_and_elaboration

modelsim: analysis
	${QUARTUS_SH} -t "${QUARTUS_ROOT_PATH}/quartus/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "${PROJECT_NAME}" "${PROJECT_NAME}"

modelsim_cli:
	${MODELSIM_BIN} -c

%.cli: ${SIM_DIR}/%.do
	${MODELSIM_BIN} -c -do "$<"

%.gui: ${SIM_DIR}/%.do
	${MODELSIM_BIN} -gui -do "$<"

%_tb:
	${MODELSIM_BIN} -gui -do "$(foreach SRC,$(VERILOG_SRC),vlog -sv {${SRC}};) vsim -t 1ps ${VSIM_ARGS} ${@}; if { [file exists ${SIM_DIR}/wave_${@}.do ] == 1} { do ${SIM_DIR}/wave_${@}.do }"

sim_fpa_mod.do:
	cd ./simulation/modelsim && ${MODELSIM_BIN} -gui -do $@