altera_devel/src/fpu16/fp_product.sv

typedef enum logic [1:0]{
    flag_none,
    flag_nan,
    flag_inf,
    flag_zero
} product_flags;

module fp_product #(parameter N=16, M=5)(input_a, input_b, output_z, clk, reset);
    localparam K=N-M-1;  // Size of mantissa

	input logic [N-1:0] input_a, input_b;
	input logic clk, reset;
	output logic [N-1:0] output_z;
	
	reg [K-1:0] a_m0, b_m0, z_m1; // mantissa
	reg [K-1:0] a_m1, b_m1, z_m2; // mantissa
	reg [K-1:0] a_m2, b_m2, z_m3; // mantissa
	reg [K-1:0] z_m4;
	
	reg [M:0] a_e0, b_e0, z_e1; // exponent
	reg [M:0] a_e1, b_e1, z_e2; // exponent
	reg [M:0] a_e2, b_e2, z_e3; // exponent
	reg [M:0] z_e4;
	
	reg a_s0, b_s0, z_s1; // sign
	reg a_s1, b_s1, z_s2; // sign
	reg a_s2, b_s2, z_s3; // sign
	reg z_s4; // sign

    product_flags flags1; // 00 for no flag, 01 for NaN, 10 for infinity, 11 for zero
	reg [2*K-1:0] z_p3; // For storing the product of the two mantissa

	always_comb begin
		// Packing the output
		output_z = {z_s4, z_e4 + (1<<M), z_m4};
	end

	always_ff @(posedge clk)
	begin
		if (~reset)
		begin
			// Unpacking the inputs
			a_s0 <= input_a[N-1];
			a_e0 <= input_a[N-2:N-2-M] - (1<<M);
			a_m0 <= input_a[N-3-M:0];
			
			b_s0 <= input_b[N-1];
			b_e0 <= input_b[N-2:N-2-M] - (1<<M);
			b_m0 <= input_b[N-3-M:0];
			
			// Untouched pipelined registers
			a_s1 <= a_s0;
			a_s2 <= a_s1;
			a_e1 <= a_e0;
			a_m1 <= a_m0;
			b_s1 <= b_s0;
			b_s2 <= b_s1;
			b_e1 <= b_e0;
			b_m1 <= b_m0;
			z_s2 <= z_s1;
			z_s4 <= z_s3;
			z_e4 <= z_e3;
			z_m2 <= z_m1;
			z_m3 <= z_m2;

			z_s3 <= a_s2 ^ b_s2; //signs xor together
			z_e3 <= a_e2 + b_e2 - (1<<M); // exponents added together subtracting one offset
			z_p3 <= a_m2 * b_m2; // mantissa multiplied together and the most significant bits are stored in the output mantissa
			z_m4 <= z_p3[2*K-1:K];

			// If input a or input b is NaN then return NaN
			if (((a_e0 ==(1<<M)) && (a_m0 != 0)) || ((b_e0 == (1<<M)) && (b_m0 != 0)))
			begin
				z_s1 <= 1;
				z_e1 <= (1 << (M+1)) - 1;
				z_m1[K-1] <= 1;
				z_m1[K-2:0] <= 0;
				flags1 <= flag_nan;
			end
			// If a is infinity then return infinity
			else if (a_e0 == (1<<M))
			begin
				// Unless b is zero, then you return NaN instead
				if (($signed(b_e0) == (-1*((1<<M)-1))) && b_m0 == 0)
				begin
					z_s1 <= 1;
					z_e1 <= (1 << (M+1)) - 1;
					z_m1[K-1] <= 1;
					z_m1[K-2:0] <= 0;
					flags1 <= flag_nan;
				end
				else
				// Returning infinity
				begin
					z_s1 <= a_s0 ^ b_s0;
					z_e1 <= (1 << (M+1)) - 1;
					z_m1 <= 0;
					flags1 <= flag_inf;
				end
			end
			// If b is infinity then return infinity
			else if (b_s0 == (1<<M))
			begin
				//Unless a is zero, then return NaN instead
				if (($signed(a_e0) == (-1*((1<<M)-1))) && a_m0 == 0)
				begin
					z_s1 <= 1;
					z_e1 <= (1 << (M+1)) - 1;
					z_m1[K-1] <= 1;
					z_m1[K-2:0] <= 0;
					flags1 <= flag_nan;
				end
				else
				// Returning infinity
				begin
					z_s1 <= a_s0 ^ b_s0;
					z_e1 <= (1 << (M+1)) - 1;
					z_m1 <= 0;
					flags1 <= flag_inf;
				end
			end
			// If either input is zero then return zero
			else if ((($signed(a_e0) == (-1*((1<<M)-1))) && (a_m0 == 0)) || (($signed(b_e0) == (-1*((1<<M)-1))) && (b_m0 == 0)))
			begin
				z_s1 <= a_s0 ^ b_s0;
				z_e1 <= 0;
				z_m1 <= 0;
				flags1 <= flag_zero;
			end
			// If b is zero then return zero
			
			// If none of the return flags have been set
			if (flags1 == flag_none)
			begin
				// If msb of a_m is 0 then shift left and reduce exponent by 1
				if (a_m1[K-1] == 0)
				begin
					a_m2 <= a_m1 << 1;
					a_e2 <= a_e1 - 1;
				end
				//Just for completion of logic
				else
				begin
					a_m2 <= a_m1;
					a_e2 <= a_e1;
				end
				// If msb of b_m is 0 then shift left and reduce exponent by 1
				if (b_m1[K-1] == 0)
				begin
					b_m2 <= b_m1 << 1;
					b_e2 <= b_e1 - 1;
				end
				//Just for completion of logic
				else
				begin
					b_m2 <= b_m1;
					b_e2 <= b_e1;
				end
			end
			
			else
			begin
				a_m2 <= a_m1;
				a_e2 <= a_e1;
				b_m2 <= b_m1;
				b_e2 <= b_e1;
				z_s3 <= z_s2;
				z_e2 <= z_e1;
				z_e3 <= z_e2;
				z_m4 <= z_m3;
				z_p3 <= 0;
			end
		end
		else
		begin
			a_s0 <= 0;
			a_e0 <= 0;
			a_m0 <= 0;
			
			a_s1 <= 0;
			a_e1 <= 0;
			a_m1 <= 0;
			
			a_s2 <= 0;
			a_e2 <= 0;
			a_m2 <= 0;
			
			b_s0 <= 0;
			b_e0 <= 0;
			b_m0 <= 0;
			
			b_s1 <= 0;
			b_e1 <= 0;
			b_m1 <= 0;
			
			b_s2 <= 0;
			b_e2 <= 0;
			b_m2 <= 0;
			
			z_s1 <= 0;
			z_e1 <= 0;
			z_m1 <= 0;
			
			z_s2 <= 0;
			z_e2 <= 0;
			z_m2 <= 0;
			
			z_s3 <= 0;
			z_e3 <= 0;
			z_m3 <= 0;
			
			z_s4 <= 0;
			z_e4 <= 0;
			z_m4 <= 0;
			
			z_p3 <= 0;
			
			flags1 <= flag_none;
		end
	end

endmodule : fp_product