altera_devel/src/root.sv

// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on

module root(
    input  clk,
    input  [1:0] keys,
    input  [3:0] switches,
    output [7:0] leds
);

    wire reset;
    wire mclk;  // Master clock for main logic
    wire pll_lock;

    assign reset = ~(keys[0] & pll_lock);
    pll pll0(
        .areset(~keys[0]),
        .inclk0(clk),
        .c0(mclk),
        .locked(pll_lock)
    );

endmodule : root


module root_tb ();
    reg  CLK50;
    reg  [1:0] KEYS;
    wire [7:0] LEDS;
    reg  [3:0] SWITCHS;

    root de0nano_0 (CLK50, KEYS, SWITCHS, LEDS);

	initial forever #10ps CLK50 = !CLK50;

    initial begin
        CLK50 = 0;
        KEYS = 2'b00;  // Keys are pull up, starting with both being pressed
        SWITCHS = 4'b0000;

        #60ps;
        KEYS = 2'b11; // Release keys
        #7000ps;
        $finish();
    end

endmodule : root_tb