Oliver Jaison
4f7fcbca22
Merge branch 'master' of https://gogs.infcof.com/4ycp/altera_devel into Oliver_FPA
|
vor 4 Jahren | |
|---|---|---|
| fpa | vor 4 Jahren | |
| scripts | vor 4 Jahren | |
| simulation | vor 4 Jahren | |
| src | vor 4 Jahren | |
| .gitignore | vor 4 Jahren | |
| Makefile | vor 4 Jahren | |
| altera_devel.qpf | vor 5 Jahren | |
| altera_devel.qsf | vor 4 Jahren | |
| readme.md | vor 4 Jahren | |
| wave_hard_sigmoid_tb.do | vor 4 Jahren |
readme.md
Altera Development Repo
Setup
Just run analysis
make analysis
if not working, specify Quartus installation directory with QUARTUS_ROOT parameter
Start modelsim GUI
make modelsim
Running testbench
Running testbench directly on GUI
make my_module_tb
This includes all modules from src/*.sv and subdirectories that contains main system verilog file with the same name as subdirectory or include.sv
Any other system verilog files in subdirectory can be included using `_include {FILE.sv} in subdirectory main file.
This command will also include saved wave instructions that are located in simulation/modelsim/wave_${my_module_tb}.do
Other testbench methods
Running testbench with defined simulation tcl script. Scripts has be located in simulation/modelsim/sim_*.do
# GUI example for simulation/modelsim/sim_root_tb.do
make sim_root_tb.gui
# Without GUI
make sim_root_tb.cli