altera_devel/Makefile

QUARTUS_ROOT := C:/intelFPGA_lite/20.1
QUARTUS_DIR = ${QUARTUS_ROOT}/quartus
MODELSIM_DIR = ${QUARTUS_ROOT}/modelsim_ase
PROJECT_NAME = altera_devel
MODELSIM_GUI = ${QUARTUS_DIR}/bin64/quartus_sh -t "${QUARTUS_DIR}/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "${PROJECT_NAME}" "${PROJECT_NAME}"
MODELSIM_BIN = ${MODELSIM_DIR}/win32aloem/vsim
QUARTUS_MACROS =  --set VERILOG_MACRO="SYNTHESIS=1"
VSIM_ARGS = -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -voptargs="+acc"

tb_file ?=
tb_dir = $(dirname "${testbench_file}")
tb_mod ?=

analysis:
	${QUARTUS_DIR}/bin64/quartus_map --read_settings_files=on --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} --analysis_and_elaboration

modelsim: analysis
	${MODELSIM_GUI}

modelsim_cli:
	${MODELSIM_BIN} -c

testbench:
	${MODELSIM_BIN} -c -do "vlog -sv +incdir+${tb_dir} {${tb_file}}; vsim -t 1ps ${VSIM_ARGS} ${tb_mod}; run -all"