/* _____ x[0] ==>| A | x_stb[0] -->| D | x_ack[0] <--| D |==> y | E |--> y_stb x[1] ==>| R |<-- y_ack x_stb[1] -->| | x_ack[1] <--|_____| */ module cadder#(parameter N=32)(clk, rst, x, x_ack, x_stb, y, y_ack, y_stb); input logic clk; input logic rst; input wire [N-1:0] x [1:0]; output logic [N-1:0] y; output x_ack[1:0]; input x_stb[1:0]; input y_ack; output y_stb; wire left_ack, left_stb; assign x_ack[0] = left_ack; assign x_ack[1] = left_ack; assign left_stb = x_stb[0] & x_stb[1]; adder add0 ( .clk(clk), .rst(rst), .input_a(x[0]), .input_b(x[1]), .input_stb(left_stb), .input_ack(left_ack), .output_z(y), .output_z_ack(y_ack), .output_z_stb(y_stb) ); endmodule : cadder /* K layers of cascade adder Example of K=3 adder: IN | K3 | K2 | K1 | OUT _ ->| | _ ->|_|-->| | _ | |--\ ->| |-->|_| | _ ->|_| \->| | _ | |-> ->| | _ /->|_| ->|_|-->| | | _ | |--/ ->| |-->|_| ->|_| [inputs] x size: 2**K left io size: 2**K */ module adder_casc#(parameter K,N=32)(clk, rst, x, y, left, right); input logic clk; input logic rst; input wire [N-1:0] x [2**K-1:0]; output logic [N-1:0] y; abus_io right; abus_io left[2**K-1:0]; wire [N-1:0] layer_w [2**K-3:0]; wire ack_w [2**K-3:0]; wire stb_w [2**K-3:0]; genvar i,j; generate for(i=0; i