// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on

module fpu32_tb();
    reg reset, clk;
    reg [31:0] input_a, input_b, result_add, result_div, result_mul;
    wire nan, overflow, underflow, zero;

    fpu_add adder(
        .aclr(reset),
        .clock(clk),
        .input_a(input_a),
        .input_b(input_b),
        .result(result_add)
    );

    fpu_div divider(
        .aclr(reset),
        .clock(clk),
        .input_a(input_a),
        .input_b(input_b),
        .result(result_div)
    );

    fpu_mul multipler(
        .aclr(reset),
        .clock(clk),
        .dataa(input_a),
        .datab(input_b),
        .result(result_mul)
    );

    task test_inputs;
        input [31:0] in_a, in_b, expected_add, expected_mul, expected_div;
        input_a = in_a;
        input_b = in_b;
        #10ps;
//        assert(exception_adder == 0);
//        assert(exception_mult == 0);
//        assert(overflow == 0);
//        assert(underflow == 0);
        if(result_add == expected_add)
            $display("PASS: %H + %H = %H", input_a, input_b, expected_add);
        else
            $error("FAIL ADD: a=%H b=%H c=%H, expected c=%H", input_a, input_b, result_add, expected_add);
        if(result_mul == expected_mul)
            $display("PASS: %H * %H = %H", input_a, input_b, expected_mul);
        else
            $error("FAIL MUL: a=%H b=%H c=%H, expected c=%H", input_a, input_b, result_mul, expected_mul);
        if(result_div == expected_div)
            $display("PASS: %H * %H = %H", input_a, input_b, expected_div);
        else
            $error("FAIL DIV: a=%H b=%H c=%H, expected c=%H", input_a, input_b, result_div, expected_div);
        #10ps;
    endtask : test_inputs

    initial forever #15ps clk = ~clk;

    initial begin
        clk = 0;
        reset = 1;
        test_inputs(32'h42480000, 32'hbf800000, 32'h42440000, 32'hc2480000, 32'hc2480000);

    end


endmodule : fpu32_tb