Pipelined testbench

simulation/modelsim/wave_floating_tb.do

@@ -0,0 +1,28 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -label CLK /floating_tb/clk
+add wave -noupdate -label RESET /floating_tb/reset
+add wave -noupdate -label {INPUT A} -radix hexadecimal /floating_tb/input_a
+add wave -noupdate -label {INPUT B} -radix hexadecimal /floating_tb/input_b
+add wave -noupdate -label ADD -radix hexadecimal /floating_tb/result_add
+add wave -noupdate -label {ADD expected} -radix hexadecimal /floating_tb/expected_add
+add wave -noupdate -label MULT -radix hexadecimal /floating_tb/result_mult
+add wave -noupdate -label {MULT expected} -radix hexadecimal /floating_tb/expected_mult
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {81 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {124 ps}

src/FPA_module_test.sv

@@ -230,31 +230,37 @@ module floating_tb;
 	reg reset, clk;
 	logic [15:0] input_a, input_b, result_add, result_mult;
 	logic [4:0] diff;
+	logic [15:0] expected_add, expected_mult;
 
 	floating_add adder1(.input_1(input_a), .input_2(input_b), .sum(result_add), .diff(diff), .clk(clk), .reset(reset));
 
 	floating_product multiplier1(.input_1(input_a), .input_2(input_b), .product(result_mult), .clk(clk), .reset(reset));
 	
 	initial forever #5 clk = ~clk;
-
+	localparam PIPELINES = 3;
 
 	reg [15:0] test_mem [29:0][3:0];
 
 	initial $readmemh("scripts/fp16_test.hex", test_mem);
 
-
 	initial begin
         static int num_err = 0;
         static int num_tests = $size(test_mem) * 2;
+
+		clk = 0;
+		reset = 1;
 		  
-		  clk = 0;
-		  reset = 1;
-		  
-		  #15;
-		  reset = 0;
-		  
+		#15;
+		reset = 0;
+
+		expected_add = 0;
+		expected_mult = 0;
 
-        for (int i=0; i < $size(test_mem); i++) begin
+        for (int i=0; i < $size(test_mem)+PIPELINES; i++) begin
+			if(i >= PIPELINES) begin
+				expected_add = test_mem[i-PIPELINES][2];
+				expected_mult = test_mem[i-PIPELINES][3];
+			end
             input_a = test_mem[i][0];
             input_b = test_mem[i][1];
 
@@ -271,7 +277,10 @@ module floating_tb;
                 num_err = num_err + 1;
             end
 
-        end
+		end
+		expected_add = 0;
+		expected_mult = 0;
+		#50;
         $display("Passed %d of %d tests", num_tests-num_err, num_tests);
         $finish();
 	end