checking fp_mult.sv

src/fpu16/fp_mult.sv

@@ -76,7 +76,7 @@ module fp_mult #(parameter N=16, M=5)(input_a, input_b, output_z, clk, reset);
 
     always_ff @(posedge clk) begin
         a_e2 <= a_e1 - a_z1;
-        a_m2 <= a_e1 << a_z1;
+        a_m2 <= a_e1 << a_z1; // a_e1 should be a_m1 maybe?
 
         b_e2 <= b_e1 - b_z1;
         b_m2 <= b_m1 << b_z1;
@@ -93,7 +93,7 @@ module fp_mult #(parameter N=16, M=5)(input_a, input_b, output_z, clk, reset);
     reg [K*2-1:0] z_p3;  // product is double mantissa
     wire [K*2-1:0] z_p3w;
 
-    assign z_p3w = a_m2 * b_m2;
+    assign z_p3w = a_m2 * b_m2; // unnecessary ?
 
     always_ff @(posedge clk) begin
         z_e3 <= a_e2 + b_e2 + 1;
@@ -155,11 +155,11 @@ module fp_mult #(parameter N=16, M=5)(input_a, input_b, output_z, clk, reset);
                 z_bits5 <= {z_bits4[1], 1'b0};
             end
             4'd2: begin
-                z_m5[1-:2] <= z_bits4;
+                z_m5[1-:2] <= z_bits4; // ?
                 z_bits5 <= 2'b00;
             end
             default : begin
-                z_m5[z_z4-1-:2] <= z_bits4;
+                z_m5[z_z4-1-:2] <= z_bits4; // ?
                 z_bits5 <= 2'b00;
             end
         endcase