pipe problems

Makefile

@@ -36,7 +36,7 @@ VSIM_ARGS = -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lns
 ## also includes subdirectories that has syntax
 ## src/{MOD_NAME}/{MOD_NAME}.sv or src/{MOD_NAME}/include.sv
 ###
-VERILOG_SRC=$(foreach SRC,$(sort $(dir $(wildcard ./src/*/*.sv))),$(wildcard $(SRC)$(basename $(SRC)).sv $(SRC)include.sv)) $(wildcard ./src/*.sv)
+VERILOG_SRC=$(foreach SRC,$(sort $(dir $(wildcard ./src/*/*.sv))),$(wildcard $(SRC)$(shell basename $(SRC)).sv $(SRC)include.sv)) $(wildcard ./src/*.sv)
 $(info VERILOG_SRC=$(VERILOG_SRC))
 SIM_DIR ?= ./simulation/modelsim
 

src/fpu16/fp_adder.sv

@@ -1,56 +1,37 @@
-module fp_adder #(parameter N=16, M=4)(input_a, input_b, output_z, clk, reset);
+module fp_adder #(parameter N=16, M=5)(input_a, input_b, output_z, clk, reset);
 	input logic [N-1:0] input_a, input_b;
 	input logic clk, reset;
 	output logic [N-1:0] output_z;
 	
-	reg [N-1:0] a, b, z;
-	reg [N-M-4:0] a_m, b_m, z_m; // mantissa
-	reg [M:0] a_e, b_e, z_e; // exponent
+	reg [N-2-M:0] a_m, b_m, z_m; // mantissa
+	reg [M-1:0] a_e, b_e, z_e; // exponent
 	reg a_s, b_s, z_s; // sign
 	
 	reg [1:0] greater; // 01 for a, 10 for b, 11 for both and 00 for neither
-	reg [M:0] abs; // For the absolute difference
-	logic [N-3-M:0] res; // For the addition result
+	reg [M:0] abs; // For the absolute difference between exponents
+	logic [N-2-M:0] res; // For the addition result
 	
-	always_ff @(posedge clk)
-	begin
-		if (reset)
-		begin
-			a <= 0;
-			b <= 0;
-			a_m <= 0;
-			b_m <= 0;
-			a_e <= 0;
-			b_e <= 0;
-			a_s <= 0;
-			b_s <= 0;
-		end
-		
-		else
-		begin
-			// Unpacking the inputs
-			a <= input_a;
-			a_m <= a[N-M-3:0];
-			a_e <= a[N-2:N-2-M];
-			a_s <= a[N-1];
-			
-			b <= input_b;
-			b_m <= b[N-M-3:0];
-			b_e <= b[N-2:N-2-M];
-			b_s <= b[N-1];
-		end
-	end
 	
 	always_ff @(posedge clk)
 	begin
 		if(~reset)
 		begin
+			// Unpacking the inputs
+			a_m <= input_a[N-M-2:0];
+			a_e <= input_a[N-2:N-M-1];
+			a_s <= input_a[N-1];
+			
+			b_m <= input_b[N-M-2:0];
+			b_e <= input_b[N-2:N-M-1];
+			b_s <= input_b[N-1];
+			
 			// If input_a has the bigger exponent then flag it with greater and find the absolute difference
 			if (a_e > b_e)
 			begin
 				greater <= 2'b01;
 				abs <= a_e - b_e;
 				z_s <= a_s;
+				z_e <= a_e;
 			end
 			// If input_a has the bigger exponent then flag it with greater and find the absolute difference
 			else if (b_e > a_e)
@@ -58,12 +39,14 @@ module fp_adder #(parameter N=16, M=4)(input_a, input_b, output_z, clk, reset);
 				greater <= 2'b10;
 				abs <= b_e - a_e;
 				z_s <= b_s;
+				z_e <= b_e;
 			end
 			// If the inputs have equal exponent
 			else
 			begin
 				greater <= 2'b00;
 				abs <= 0;
+				z_e <= a_e;
 				// Assigning the overall sign based on the difference between the mantissa
 				if(a_m > b_m)
 				begin
@@ -78,40 +61,26 @@ module fp_adder #(parameter N=16, M=4)(input_a, input_b, output_z, clk, reset);
 					z_s <= 0;
 				end
 			end
-		end
-		
-		else
-		begin
-			greater <= 2'b00;
-			abs <= 0;
-			z_s <= 0;
-		end
-	end
-	
-	always_ff @(posedge clk)
-	begin
-		if(~reset)
-		begin
 			// Condition for overflow is that it sets the output to the larger input
-			if (abs > N-2-M) // Shifting by N-2-M would give 0
+			if (abs > N-1-M) // Shifting by N-1-M would give 0
 			begin
 				if (greater == 2'b01)
 				begin
-					z <= a; // Input a is larger and is translated to the output
+					z_m <= a_m; // Input a is larger and is translated to the output
 				end
 				else if (greater == 2'b10)
 				begin
-					z <= b; // Input b is larger and is translated to the output
+					z_m <= b_m; // Input b is larger and is translated to the output
 				end
-				else
+				else // Shouldn't happen as abs should be 0 for this to occur
 				begin
 					if (a_m >= b_m)
 					begin
-						z <= a; // Equal exponents but a has the larger mantissa
+						z_m <= a_m; // Equal exponents but a has the larger mantissa
 					end
 					else if (b_m > a_m)
 					begin
-						z <= b; // Equal exponents but b has the larger mantissa
+						z_m <= b_m; // Equal exponents but b has the larger mantissa
 					end
 				end
 			end
@@ -176,28 +145,31 @@ module fp_adder #(parameter N=16, M=4)(input_a, input_b, output_z, clk, reset);
 				// Assigning the mantissa of output the the sum of input mantissa
 				z_m <= res;
 			end
+			output_z[N-1] <= z_s;
+			output_z[N-2:N-1-M] <= z_e;
+			output_z[N-2-M:0] <= z_m;
 		end
-		
+
+	
 		else
 		begin
-			z <= 0;
+			a_s <= 0;
+			a_e <= 0;
+			a_m <= 0;
+			
+			b_s <= 0;
+			b_e <= 0;
+			b_m <= 0;
+			
+			z_s <= 0;
+			z_e <= 0;
 			z_m <= 0;
+			
+			greater <= 0;
+			abs <= 0;
 			res <= 0;
-		end
-	end
-	
-	always_ff @(posedge clk)
-	begin
-		if (~reset)
-		// Packing the output back together
-		begin
-			z[N-1] <= z_s;
-			z[N-2:N-2-M] <= z_e;
-			z[N-3-M:0] <= z_m;
-		end
-		else
-		begin
-			z <= 0;
+			
+			output_z <= 0;
 		end
 	end
 endmodule : fp_adder

src/fpu16/fpu16.sv

@@ -48,7 +48,7 @@ module fpu16_tb;
 
 			if(result_mult != test_mem[i][3]) begin
                 if(num_err < 20)
-                    $display("FAIL MULTIPLY: %H + %H = %H, expected %H", input_a, input_b, result_mult, test_mem[i][3]);
+                    $display("FAIL MULTIPLY: %H x %H = %H, expected %H", input_a, input_b, result_mult, test_mem[i][3]);
                 num_err = num_err + 1;
             end