Working cascade!

src/fpu32/adder.v

@@ -2,6 +2,24 @@
 //Copyright (C) Jonathan P Dawson 2013
 //2013-12-12
 
+typedef enum logic [3:0] {
+  get_a,
+  get_b,
+  unpack,
+  special_cases,
+  align,
+  add_0,
+  add_1,
+  normalise_1,
+  normalise_2,
+  round,
+  pack,
+  put_z,
+  get_input
+
+} state_type;
+
+
 module adder(
         clk,
         rst,
@@ -31,21 +49,7 @@ module adder(
   reg       [31:0] s_output_z;
   reg       s_input_ack;
 
-  reg       [3:0] state;
-	
-  parameter get_a         = 4'd0,
-            get_b         = 4'd1,
-            unpack        = 4'd2,
-            special_cases = 4'd3,
-            align         = 4'd4,
-            add_0         = 4'd5,
-            add_1         = 4'd6,
-            normalise_1   = 4'd7,
-            normalise_2   = 4'd8,
-            round         = 4'd9,
-            pack          = 4'd10,
-            put_z         = 4'd11,
-            get_input     = 4'd12;
+  state_type state;
 
   reg       [31:0] a, b, z;
   reg       [26:0] a_m, b_m;

src/fpu32/fpu32.sv

@@ -1,4 +1,4 @@
-`include "adder.v"
+`include "adder.sv"
 `include "mult.v"
 
 // synopsys translate_off

src/neural/comp.sv

@@ -1,44 +1,6 @@
 `include "../blocks/abus.sv"
 `include "../fpu32/fpu32.sv"
 
-/*
-            _____
-     x0 -->|  A  |
-  abus0 <->|  D  |
-           |  D  |--> y0
-           |  E  |<-> abus_y
-     x1 -->|  R  |
-  abus0 <->|_____|
-
-*/
-
-module abus_adder#(parameter N=32)(x, clk, rst, y, left0, left1, right);
-    input logic clk;
-    input logic rst;
-    input wire [N-1:0] x [1:0];
-    output logic [N-1:0] y;
-    abus_io left0;
-    abus_io left1;
-    abus_io right;
-
-    wire left_ack, left_stb;
-    assign left0.ack = left_ack;
-    assign left1.ack = left_ack;
-    assign left_stb = left0.stb & left1.stb;
-
-    adder add0 (
-        .clk(clk),
-        .rst(rst),
-        .input_a(x[0]),
-        .input_b(x[1]),
-        .input_stb(left_stb),
-        .input_ack(left_ack),
-        .output_z(y),
-        .output_z_ack(right.ack),
-        .output_z_stb(right.stb)
-    );
-endmodule : abus_adder
-
 /*
               _____
      x[0] ==>|  A  |
@@ -78,39 +40,6 @@ module cadder#(parameter N=32)(clk, rst, x, x_ack, x_stb, y, y_ack, y_stb);
     );
 endmodule : cadder
 
-// module adder4to2_tb();
-//     logic clk, rst;
-//
-//     logic [31:0] x [3:0];
-//     logic [31:0] y [1:0];
-//     abus_io inputBus();
-//     abus_io outputBus();
-//
-//     adder4to2 adder_casc(.clk(clk), .rst(rst), .x(x), .y(y), .left(inputBus.right), .right(outputBus.left));
-//     initial forever #5 clk = ~clk;
-//     initial begin
-//         $display("Testing adder4to2");
-//         clk = 0;
-//         rst = 1;
-//         inputBus.stb = 0;
-//         outputBus.ack = 0;
-//         #20
-//         rst = 0;
-//         x = {'h41388000, 'h407c0000, 'h42480000, 'h42460000};
-//         inputBus.stb = 1;
-//         wait(inputBus.ack == 1);
-//         #15 inputBus.stb = 0;
-//
-//         wait(outputBus.stb == 1);
-//         outputBus.ack = 1;
-//         assert(y[0] == 'h42c70000);
-//         assert(y[1] == 'h41778000);
-//         wait(outputBus.stb == 0);
-//         outputBus.ack = 0;
-//     end
-//
-// endmodule : adder4to2_tb
-
 /*
   K layers of cascade adder
   
@@ -163,9 +92,6 @@ module adder_casc#(parameter K,N=32)(clk, rst, x, y, left, right);
                       .x_stb({left[j*2].stb, left[j*2+1].stb}),
                       .y_ack(ack_w[j]),
                       .y_stb(stb_w[j])
-                      // .left0(left[j*2].right),
-                      // .left1(left[j*2+1].right),
-                      // .right(bus_w[j].left)
                     );
                 end
             end
@@ -182,9 +108,6 @@ module adder_casc#(parameter K,N=32)(clk, rst, x, y, left, right);
                     .x_stb({stb_w[s0], stb_w[s1]}),
                     .y_ack(right.ack),
                     .y_stb(right.stb)
-                    // .left0(bus_w[s0].right),
-                    // .left1(bus_w[s1].right),
-                    // .right(right)
                 );
             end
             // Middle layers
@@ -204,28 +127,6 @@ module adder_casc#(parameter K,N=32)(clk, rst, x, y, left, right);
                         .y_ack(ack_w[iy]),
                         .y_stb(stb_w[iy])
                     );
-
-                    // // localparam m = i - 1;
-                    // // localparam s0 = 2.0**(K-1.0) * (2.0**m-1.0)/2.0**m;
-                    // // localparam s = s0 + j;
-                    // localparam s = $floor((2.0**(K-1.0) * (2.0**(i-1)-1.0)/2.0**(i-1))+j);
-                    // localparam ix = s*2;
-                    // localparam ix1 = s*2+1;
-                    // localparam iy = s+2**(K-1);
-                    // abus_adder b(
-                    //   .clk(clk),
-                    //   .rst(rst),
-                    //   // .x(bus_w[index_x+:2]),
-                    // //   // .y(bus_w[(2**(K-1)*((2**(i-2)-1)/2**(i-2)) + j)+2**(K-1)].right),
-                    // //   // .left0(bus_w[(2**(K-1)*((2**(i-2)-1)/2**(i-2)) + j)*2].right),
-                    // //   // .left1(bus_w[(2**(K-1)*((2**(i-2)-1)/2**(i-2)) + j)*2+1].right),
-                    // //   // .right(bus_w[(2**(K-1)*((2**(i-2)-1)/2**(i-2)) + j)+2**(K-1)].left)
-                    //   .x(layer_w[ix+:2]),
-                    //   .y(layer_w[iy]),
-                    //   .left0(bus_v[ix].right),
-                    //   .left1(bus_v[ix1].right),
-                    //   .right(bus_v[iy].left)
-                    // );
                 end
             end
         end
@@ -239,21 +140,22 @@ module adder_casc_tb();
     localparam K=4;
     logic [31:0] x [2**K-1:0];
     logic [31:0] y;
+    logic ack [2**K-1:0];
+    logic stb [2**K-1:0];
+
     abus_io input_ios[2**K-1:0]();
     abus_io output_io();
     
-    virtual abus_io input_vios[2**K-1:0];
     genvar k;
     generate
-        for(k=0; k<2**K; k++) begin : map_generator
-            initial begin : map_physical2virtual
-                input_vios[k] = input_ios[k];
-            end : map_physical2virtual
+        for(k=0; k<2**K; k++) begin : io_mapper
+            assign input_ios[k].stb = stb[k];
+            assign ack[k] = input_ios[k].ack;
         end
     endgenerate
     
     
-    adder_casc#(.K(K)) adder_casc0(.clk(clk), .rst(rst), .x(x), .y(y), .left(input_ios), .right(output_io.left));    
+    adder_casc#(.K(K)) adder_casc0(.clk(clk), .rst(rst), .x(x), .y(y), .left(input_ios), .right(output_io.left));
     initial forever #5 clk = ~clk;
     initial begin
         
@@ -261,23 +163,24 @@ module adder_casc_tb();
         clk = 0;
         rst = 1;
         
-        foreach(input_vios[i]) input_vios[i].stb = 0;
+        foreach(stb[i]) stb[i] = 0;
         output_io.ack = 0;
         #20
         rst = 0;
         // Initialise with floating point 2**i
         foreach(x[i]) x[i] = ('h400 + (i*8)) << 20;
+        foreach(stb[i]) stb[i] = 1;
+
         fork
-            foreach(input_vios[i]) begin
+            foreach(ack[i]) begin
                 fork
-                    input_vios[i].stb = 1;
-                    wait(input_vios[i].ack == 1);
-                    #10
-                    input_vios[i].stb = 0;
+                    wait(ack[i] == 1);
+                    #20
+                    stb[i] = 0;
                 join
             end
         join
-        #20 
+        #20
         
         wait(output_io.stb == 1);
         output_io.ack = 1;