New testbench execution method

.gitignore

@@ -11,6 +11,7 @@
 !*.sv
 !*.py
 !sim_*.do
+!wave_*_tb.do
 !*.qip
 
 # Making sure nothing from there will be picked up

Makefile

@@ -31,11 +31,13 @@ QUARTUS_MACROS = --set VERILOG_MACRO="SYNTHESIS=1"
 VSIM_ARGS = -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -voptargs="+acc"
 
 
-### Optional parameters
-tb_file ?=
-tb_dir = $(dirname "${testbench_file}")
-tb_mod ?=
-do_file ?=
+### VERILOG SOURCE FILES
+## It finds all verilog files in src/*.sv and
+## also includes subdirectories that has syntax
+## src/{MOD_NAME}/{MOD_NAME}.sv or src/{MOD_NAME}/include.sv
+###
+VERILOG_SRC=$(foreach SRC,$(sort $(dir $(wildcard ./src/*/*.sv))),$(wildcard $(SRC)$(shell basename $(SRC)).sv $(SRC)include.sv)) $(wildcard ./src/*.sv)
+$(info VERILOG_SRC=$(VERILOG_SRC))
 SIM_DIR ?= ./simulation/modelsim
 
 ### ================================================================
@@ -57,8 +59,8 @@ modelsim_cli:
 %.gui: ${SIM_DIR}/%.do
 	${MODELSIM_BIN} -gui -do "$<"
 
-testbench:
-	${MODELSIM_BIN} -c -do "vlog -sv +incdir+${tb_dir} {${tb_file}}; vsim -t 1ps ${VSIM_ARGS} ${tb_mod}; run -all"
+%_tb:
+	${MODELSIM_BIN} -gui -do "$(foreach SRC,$(VERILOG_SRC),vlog -sv {${SRC}};) vsim -t 1ps ${VSIM_ARGS} ${@}; if { [file exists ${SIM_DIR}/wave_${@}.do ] == 1} { do ${SIM_DIR}/wave_${@}.do }"
 
 sim_fpa_mod.do:
 	cd ./simulation/modelsim && ${MODELSIM_BIN} -gui -do $@

readme.md

@@ -14,12 +14,19 @@ make modelsim
 
 ### Running testbench
 
-This will run test testbench in console without opening modelsim GUI
+Running testbench directly on GUI
 ```bash
-make tb_file=${file} tb_mod=${module} testbench
-# Example
-make tb_file=./src/root.sv tb_mod=root_tb testbench
+make my_module_tb
 ```
+This includes all modules from src/*.sv and subdirectories that contains __main__ system verilog file with the same name as 
+subdirectory or include.sv
+
+Any other system verilog files in subdirectory can be included using `` `_include {FILE.sv} `` in subdirectory main file. 
+
+This command will also include saved wave instructions that are located in **simulation/modelsim/wave_${my_module_tb}.do** 
+
+
+### Other testbench methods
 Running testbench with defined simulation tcl script.
 Scripts has be located in **simulation/modelsim/sim_\*.do**
 ```bash
@@ -27,4 +34,6 @@ Scripts has be located in **simulation/modelsim/sim_\*.do**
 make sim_root_tb.gui
 # Without GUI
 make sim_root_tb.cli
-```
+```
+
+

simulation/modelsim/wave_floating32_tb.do

@@ -0,0 +1,24 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -label INPUT_A -radix float32 /floating32_tb/input_a
+add wave -noupdate -label INPUT_B -radix float32 /floating32_tb/input_b
+add wave -noupdate -label RESULT_ADD -radix float32 /floating32_tb/result_add
+add wave -noupdate -label RESULT_MULT -radix float32 /floating32_tb/result_mult
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+quietly wave cursor active 0
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {47 ps}

src/fpu32/adder.sv

@@ -3,21 +3,19 @@
 //2013-12-12
 
 typedef enum logic [3:0] {
-  get_a,
-  get_b,
-  unpack,
-  special_cases,
-  align,
+  add_unpack,
+  add_special,
+  add_align,
   add_0,
   add_1,
-  normalise_1,
-  normalise_2,
-  round,
-  pack,
-  put_z,
-  get_input
+  add_norm_0,
+  add_norm_1,
+  add_round,
+  add_pack,
+  add_output,
+  add_input
 
-} state_type;
+} adder_state;
 
 
 module adder(
@@ -49,7 +47,7 @@ module adder(
   reg       [31:0] s_output_z;
   reg       s_input_ack;
 
-  state_type state;
+  adder_state state;
 
   reg       [31:0] a, b, z;
   reg       [26:0] a_m, b_m;
@@ -82,20 +80,20 @@ module adder(
 //        end
 //      end
 
-      get_input:
+      add_input:
       begin
         s_input_ack <= 1;
         if (s_input_ack && input_stb) begin
           a <= input_a;
           b <= input_b;
           s_input_ack <= 0;
-          state <= unpack;
+          state <= add_unpack;
         end
       end
 
 
 
-      unpack:
+      add_unpack:
       begin
         a_m <= {a[22 : 0], 3'd0};
         b_m <= {b[22 : 0], 3'd0};
@@ -103,18 +101,18 @@ module adder(
         b_e <= b[30 : 23] - 127;
         a_s <= a[31];
         b_s <= b[31];
-        state <= special_cases;
+        state <= add_special;
       end
 
-      special_cases:
+      add_special:
       begin
         //if a is NaN return a
         if (a_e == 128 && a_m != 0) begin
           z <= {a_s, 8'hff, a[22], a[21:0]};
-          state <= put_z;
+          state <= add_output;
         end else if (b_e == 128 && b_m != 0) begin
           z <= {b_s, 8'hff, b[22:0]};
-          state <= put_z;
+          state <= add_output;
         //if a is inf return inf
         end else if (a_e == 128 && a_m == 0) begin
           z[31] <= a_s;
@@ -127,31 +125,31 @@ module adder(
               z[22] <= 1;
               z[21:0] <= 0;
           end
-          state <= put_z;
+          state <= add_output;
         //if b is inf return inf
         end else if (b_e == 128 && b_m == 0) begin
           z[31] <= b_s;
           z[30:23] <= 255;
           z[22:0] <= 0;
-          state <= put_z;
+          state <= add_output;
         //if a is zero return b
         end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
           z[31] <= a_s & b_s;
           z[30:23] <= b_e[7:0] + 127;
           z[22:0] <= b_m[26:3];
-          state <= put_z;
+          state <= add_output;
         //if a is zero return b
         end else if (($signed(a_e) == -127) && (a_m == 0)) begin
           z[31] <= b_s;
           z[30:23] <= b_e[7:0] + 127;
           z[22:0] <= b_m[26:3];
-          state <= put_z;
+          state <= add_output;
         //if b is zero return a
         end else if (($signed(b_e) == -127) && (b_m == 0)) begin
           z[31] <= a_s;
           z[30:23] <= a_e[7:0] + 127;
           z[22:0] <= a_m[26:3];
-          state <= put_z;
+          state <= add_output;
         end else begin
           //Denormalised Number
           if ($signed(a_e) == -127) begin
@@ -165,11 +163,11 @@ module adder(
           end else begin
             b_m[26] <= 1;
           end
-          state <= align;
+          state <= add_align;
         end
       end
 
-      align:
+      add_align:
       begin
         if ($signed(a_e) > $signed(b_e)) begin
           b_e <= b_e + 1;
@@ -216,10 +214,10 @@ module adder(
           round_bit <= sum[1];
           sticky <= sum[0];
         end
-        state <= normalise_1;
+        state <= add_norm_0;
       end
 
-      normalise_1:
+      add_norm_0:
       begin
         if (z_m[23] == 0 && $signed(z_e) > -126) begin
           z_e <= z_e - 1;
@@ -228,11 +226,11 @@ module adder(
           guard <= round_bit;
           round_bit <= 0;
         end else begin
-          state <= normalise_2;
+          state <= add_norm_1;
         end
       end
 
-      normalise_2:
+      add_norm_1:
       begin
         if ($signed(z_e) < -126) begin
           z_e <= z_e + 1;
@@ -241,11 +239,11 @@ module adder(
           round_bit <= guard;
           sticky <= sticky | round_bit;
         end else begin
-          state <= round;
+          state <= add_round;
         end
       end
 
-      round:
+      add_round:
       begin
         if (guard && (round_bit | sticky | z_m[0])) begin
           z_m <= z_m + 1;
@@ -253,10 +251,10 @@ module adder(
             z_e <=z_e + 1;
           end
         end
-        state <= pack;
+        state <= add_pack;
       end
 
-      pack:
+      add_pack:
       begin
         z[22 : 0] <= z_m[22:0];
         z[30 : 23] <= z_e[7:0] + 127;
@@ -273,23 +271,23 @@ module adder(
           z[30 : 23] <= 255;
           z[31] <= z_s;
         end
-        state <= put_z;
+        state <= add_output;
       end
 
-      put_z:
+      add_output:
       begin
         s_output_z_stb <= 1;
         s_output_z <= z;
         if (s_output_z_stb && output_z_ack) begin
           s_output_z_stb <= 0;
-          state <= get_input;
+          state <= add_input;
         end
       end
 
     endcase
 
     if (rst == 1) begin
-      state <= get_input;
+      state <= add_input;
       s_input_ack <= 0;
       s_output_z_stb <= 0;
     end

src/fpu32/mult.v

@@ -3,22 +3,20 @@
 //2013-12-12
 
 typedef enum logic [3:0] {
-  get_a,
-  get_b,
-  unpack,
-  special_cases,
-  normalise_a,
-  normalise_b,
-  multiply_0,
-  multiply_1,
-  normalise_1,
-  normalise_2,
-  round,
-  pack,
-  put_z,
-  get_input
+  mul_unpack,
+  mul_special,
+  mul_norm_a,
+  mul_norm_b,
+  mul_0,
+  mul_1,
+  mul_norm_1,
+  mul_norm_2,
+  mul_round,
+  mul_pack,
+  mul_output,
+  mul_input
 
-} state_type;
+} mult_state;
 
 
 module multiplier(
@@ -50,7 +48,7 @@ module multiplier(
   reg       [31:0] s_output_z;
   reg       s_input_ack;
 
-  state_type state;
+  mult_state state;
 
   reg       [31:0] a, b, z;
   reg       [23:0] a_m, b_m, z_m;
@@ -84,18 +82,18 @@ module multiplier(
 //        end
 //      end
 
-      get_input:
+      mul_input:
       begin
         s_input_ack <= 1;
         if (s_input_ack && input_stb) begin
           a <= input_a;
           b <= input_b;
           s_input_ack <= 0;
-          state <= unpack;
+          state <= mul_unpack;
         end
       end
 
-      unpack:
+      mul_unpack:
       begin
         a_m <= a[22 : 0];
         b_m <= b[22 : 0];
@@ -103,10 +101,10 @@ module multiplier(
         b_e <= b[30 : 23] - 127;
         a_s <= a[31];
         b_s <= b[31];
-        state <= special_cases;
+        state <= mul_special;
       end
 
-      special_cases:
+      mul_special:
       begin
         //if a is NaN or b is NaN return NaN
         if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
@@ -114,7 +112,7 @@ module multiplier(
           z[30:23] <= 255;
           z[22] <= 1;
           z[21:0] <= 0;
-          state <= put_z;
+          state <= mul_output;
         //if a is inf return inf
         end else if (a_e == 128) begin
           z[31] <= a_s ^ b_s;
@@ -127,7 +125,7 @@ module multiplier(
             z[22] <= 1;
             z[21:0] <= 0;
           end
-          state <= put_z;
+          state <= mul_output;
         //if b is inf return inf
         end else if (b_e == 128) begin
           z[31] <= a_s ^ b_s;
@@ -140,19 +138,19 @@ module multiplier(
             z[22] <= 1;
             z[21:0] <= 0;
           end
-          state <= put_z;
+          state <= mul_output;
         //if a is zero return zero
         end else if (($signed(a_e) == -127) && (a_m == 0)) begin
           z[31] <= a_s ^ b_s;
           z[30:23] <= 0;
           z[22:0] <= 0;
-          state <= put_z;
+          state <= mul_output;
         //if b is zero return zero
         end else if (($signed(b_e) == -127) && (b_m == 0)) begin
           z[31] <= a_s ^ b_s;
           z[30:23] <= 0;
           z[22:0] <= 0;
-          state <= put_z;
+          state <= mul_output;
         end else begin
           //Denormalised Number
           if ($signed(a_e) == -127) begin
@@ -166,48 +164,48 @@ module multiplier(
           end else begin
             b_m[23] <= 1;
           end
-          state <= normalise_a;
+          state <= mul_norm_a;
         end
       end
 
-      normalise_a:
+      mul_norm_a:
       begin
         if (a_m[23]) begin
-          state <= normalise_b;
+          state <= mul_norm_b;
         end else begin
           a_m <= a_m << 1;
           a_e <= a_e - 1;
         end
       end
 
-      normalise_b:
+      mul_norm_b:
       begin
         if (b_m[23]) begin
-          state <= multiply_0;
+          state <= mul_0;
         end else begin
           b_m <= b_m << 1;
           b_e <= b_e - 1;
         end
       end
 
-      multiply_0:
+      mul_0:
       begin
         z_s <= a_s ^ b_s;
         z_e <= a_e + b_e + 1;
         product <= a_m * b_m * 4;
-        state <= multiply_1;
+        state <= mul_1;
       end
 
-      multiply_1:
+      mul_1:
       begin
         z_m <= product[49:26];
         guard <= product[25];
         round_bit <= product[24];
         sticky <= (product[23:0] != 0);
-        state <= normalise_1;
+        state <= mul_norm_1;
       end
 
-      normalise_1:
+      mul_norm_1:
       begin
         if (z_m[23] == 0) begin
           z_e <= z_e - 1;
@@ -216,11 +214,11 @@ module multiplier(
           guard <= round_bit;
           round_bit <= 0;
         end else begin
-          state <= normalise_2;
+          state <= mul_norm_2;
         end
       end
 
-      normalise_2:
+      mul_norm_2:
       begin
         if ($signed(z_e) < -126) begin
           z_e <= z_e + 1;
@@ -229,11 +227,11 @@ module multiplier(
           round_bit <= guard;
           sticky <= sticky | round_bit;
         end else begin
-          state <= round;
+          state <= mul_round;
         end
       end
 
-      round:
+      mul_round:
       begin
         if (guard && (round_bit | sticky | z_m[0])) begin
           z_m <= z_m + 1;
@@ -241,10 +239,10 @@ module multiplier(
             z_e <=z_e + 1;
           end
         end
-        state <= pack;
+        state <= mul_pack;
       end
 
-      pack:
+      mul_pack:
       begin
         z[22 : 0] <= z_m[22:0];
         z[30 : 23] <= z_e[7:0] + 127;
@@ -258,23 +256,23 @@ module multiplier(
           z[30 : 23] <= 255;
           z[31] <= z_s;
         end
-        state <= put_z;
+        state <= mul_output;
       end
 
-      put_z:
+      mul_output:
       begin
         s_output_z_stb <= 1;
         s_output_z <= z;
         if (s_output_z_stb && output_z_ack) begin
           s_output_z_stb <= 0;
-          state <= get_input;
+          state <= mul_input;
         end
       end
 
     endcase
 
     if (rst == 1) begin
-      state <= get_input;
+      state <= mul_input;
       s_input_ack <= 0;
       s_output_z_stb <= 0;
     end

src/neural/comp.sv

@@ -1,6 +1,3 @@
-`include "../blocks/abus.sv"
-`include "../fpu32/fpu32.sv"
-
 /*
               _____
      x[0] ==>|  A  |