debugging pipeline

src/FPA_module_test.sv

@@ -30,7 +30,7 @@ module floating_add #(parameter N=16, M=4)(input_1, input_2, sum, diff, clk, res
 			D0[6] = 0; // abs
 			D0[7] = 0; // res
 		end
-	pipe pipe0(.clk(clk), .reset(reset), .D(D0), .Q(Q0));
+	pipe#(.N(N-1), .K(7)) pipe0(.clk(clk), .reset(reset), .D(D0), .Q(Q0));
 	
 	
 	always_comb
@@ -72,7 +72,7 @@ module floating_add #(parameter N=16, M=4)(input_1, input_2, sum, diff, clk, res
 		end
 		
 		//Second pipeline stage 1
-		pipe pipe1(.clk(clk), .reset(reset), .D(Q0), .Q(Q1));
+		pipe#(.N(N-1), .K(7)) pipe1(.clk(clk), .reset(reset), .D(Q0), .Q(Q1));
 		
 	always_comb
 		begin
@@ -145,7 +145,7 @@ module floating_add #(parameter N=16, M=4)(input_1, input_2, sum, diff, clk, res
 		end
 		
 		// Final pipeline stage 
-		pipe pipe2(.clk(clk), .reset(reset), .D(Q1), .Q(Q2));
+		pipe#(.N(N-1), .K(7)) pipe2(.clk(clk), .reset(reset), .D(Q1), .Q(Q2));
 		assign sum = Q2[2];
 		assign diff = Q2[3];
 endmodule : floating_add
@@ -178,14 +178,14 @@ module floating_product #(parameter N=16, M=4)(input_1, input_2, product, clk, r
 			D0[4] = 0; // mult
 		end
 		
-	pipe pipe0(.clk(clk), .reset(reset), .D(D0), .Q(Q0));
+	pipe#(.N(2*(N-3-M)), .K(4)) pipe0(.clk(clk), .reset(reset), .D(D0), .Q(Q0));
 
 	// We have assigned an {M+1} bit exponent so we must have a 2^{M} offset
 	assign Q0[3] = Q0[0][N-2:N-2-M] + Q0[1][N-2:N-2-M];
 	assign Q0[2][N-2:N-2-M] = Q0[3] - (1'b1 << M) + 2;
 	
 	// Second pipeline stage
-	pipe pipe1(.clk(clk), .reset(reset), .D(Q0), .Q(Q1));
+	pipe#(.N(2*(N-3-M)), .K(4)) pipe1(.clk(clk), .reset(reset), .D(Q0), .Q(Q1));
 
 	always_comb
 		begin