Script for starting tb

Makefile

@@ -57,4 +57,7 @@ sim_gui:
 	cd ./simulation/modelsim && ${MODELSIM_BIN} -gui -do "${do_file}"
 
 testbench:
-	${MODELSIM_BIN} -c -do "vlog -sv +incdir+${tb_dir} {${tb_file}}; vsim -t 1ps ${VSIM_ARGS} ${tb_mod}; run -all"
+	${MODELSIM_BIN} -c -do "vlog -sv +incdir+${tb_dir} {${tb_file}}; vsim -t 1ps ${VSIM_ARGS} ${tb_mod}; run -all"
+
+sim_fpa_mod.do:
+	cd ./simulation/modelsim && ${MODELSIM_BIN} -gui -do $@

altera_devel.qsf

@@ -77,6 +77,7 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name SYSTEMVERILOG_FILE src/fpu32/fpu32.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/root.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/FPA_module_test.sv
 set_global_assignment -name QIP_FILE src/fpu32/fpu_add.qip
 set_global_assignment -name QIP_FILE src/fpu32/fpu_div.qip
 set_global_assignment -name QIP_FILE src/fpu32/fpu_mul.qip

simulation/modelsim/sim_fpa_mod.do

@@ -0,0 +1,43 @@
+#transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+set rootdir [pwd]/../..
+puts "Root Directory $rootdir"
+vlib rtl_work
+vmap work rtl_work
+
+vlog -sv -work work +incdir+${rootdir}/src ${rootdir}/src/FPA_module_test.sv
+vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" floating_tb
+
+view structure
+view signals
+
+add wave -position end -label CLK  sim:/floating_tb/clk
+add wave -position end -label RESET  sim:/floating_tb/reset
+add wave -position end -label INPUT_A -radix hex sim:/floating_tb/input_a
+add wave -position end -label INPUT_B -radix hex sim:/floating_tb/input_b
+add wave -position end -label Result_ADD -radix hex sim:/floating_tb/result_add
+add wave -position end -label Result_MULT -radix hex sim:/floating_tb/result_mult
+
+add log sim:/floating_tb/test_mem
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+quietly wave cursor active 0
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {1 ns}
+

src/FPA_module_test.sv

@@ -206,7 +206,7 @@ module floating_tb;
 
 	reg [15:0] test_mem [29:0][3:0];
 
-	initial $readmemh("..\..\scripts\fp16_test.hex", test_mem);
+	initial $readmemh("../../scripts/fp16_test.hex", test_mem);
 
 
 	initial begin

src/root.sv

@@ -1,7 +1,6 @@
 // synopsys translate_off
 `timescale 1 ps / 1 ps
 // synopsys translate_on
-`include "FPA_module_test.sv"
 
 module root(
     input  clk,