fixed pipelining?

src/FPA_module_test.sv

@@ -197,28 +197,30 @@ module floating_product #(parameter N=16, M=4)(input_1, input_2, product, clk, r
 		end
 	
 	//Final Pipeline stage
-	pipe#(.N(2*N-3-M), .K(4)) pipe2(.clk(clk), .reset(reset), .D(Q1), .Q(Q2));
+	pipe#(.N(2*(N-3-M)), .K(4)) pipe2(.clk(clk), .reset(reset), .D(Q1), .Q(Q2));
 	assign product = Q2[2][N-1:0];
 endmodule : floating_product
 
 
 
-module pipe #(parameter N=16)(clk, reset, Q, D);
+module pipe #(parameter N, K)(clk, reset, Q, D);
 	input logic clk, reset;
-	input logic [N-1:0] D;
-	output reg [N-1:0] Q;
-	reg [N-1:0] in_pipe;
+	input logic [N:0] D [K:0];
+	output reg [N:0] Q [K:0];
+	reg [N:0] in_pipe [K:0];
 	
-	always @(posedge clk or negedge reset)
+	always_ff @(posedge clk or negedge reset)
 		begin
-			if(reset) in_pipe = 0;
-			else in_pipe = D;
-		end
-	
-	always @(posedge clk or negedge reset)
-		begin
-			if(reset) Q = 0;
-			else Q = in_pipe;
+			if(reset) 
+				begin
+					in_pipe <= '{default:0};
+					Q <= '{default:0};
+				end
+			else 
+				begin
+					in_pipe[N:0] <= D[N:0];
+					Q[N:0] <= in_pipe[N:0];
+				end
 		end
 endmodule : pipe
 
@@ -229,9 +231,9 @@ module floating_tb;
 	logic [15:0] input_a, input_b, result_add, result_mult;
 	logic [4:0] diff;
 
-	floating_add adder1(.input_1(input_a), .input_2(input_b), .sum(result_add), .diff(diff));
+	floating_add adder1(.input_1(input_a), .input_2(input_b), .sum(result_add), .diff(diff), .clk(clk), .reset(reset));
 
-	floating_product multiplier1(.input_1(input_a), .input_2(input_b), .product(result_mult));
+	floating_product multiplier1(.input_1(input_a), .input_2(input_b), .product(result_mult), .clk(clk), .reset(reset));
 
 
 	reg [15:0] test_mem [29:0][3:0];