Debugging Test Vectors

scripts/fpu_test_gen.py

@@ -40,4 +40,4 @@ def generate_fp_vector(cases, filename, dtype=np.float16, big_endian=False):
 
 
 if __name__ == '__main__':
-    generate_fp_vector(10000, 'fp32_test.hex', dtype=np.float32, big_endian=True)
+    generate_fp_vector(30, 'fp16_test.hex', dtype=np.float16, big_endian=True)

src/FPA_module_test.sv

@@ -1,7 +1,7 @@
 module floating_add #(parameter N=16, M=4)(a, b, c, flag_double);
 	input logic [N-1:0] a, b; 
 	output logic [N-1:0] c;
-	output flag_double;
+	output logic flag_double;
 
 	logic flag_a;
 	logic flag_b;
@@ -57,6 +57,7 @@ module floating_add #(parameter N=16, M=4)(a, b, c, flag_double);
 					if (flag_a & ~flag_b) c = a;
 					else if (~flag_a & flag_b) c = b;
 					else c = a;
+					flag_double = 0;
 				end
 			else
 				begin
@@ -155,41 +156,41 @@ endmodule : floating_product
 
 
 
-module Integer2FP #(parameter N = 16, M = 4)(in, out);
-// Considering we have a 10 bit mantissa, I assume 11 bit integer input
-	input logic [N-2-M:0] in;
-	output logic [N-1:0] out;
-
-	logic shift_counter = 0;
-
-	// Saving the sign
-	assign out[N-1] = in[N-2-M];
-
-	always_comb
-		begin
-			// Shifting the absolute value until MSB is 1 and keeping track of the number of shifts
-			while (!in[N-3-M])
-				begin
-					shift_counter = shift_counter + 1;
-					in[N-3-M] = in[N-3-M:0] << 1;
-				end
-			// Assigning the mantissa as the shifted absolute value
-			// Assigning the exponent as the number of shifts -  a constant 137
-			out[N-3-M:0] = in[N-3-M:0];
-			out[N-2:N-2-M] = shift_counter - 137;
-		end
-endmodule : Integer2FP
-
-
-
-module FP2Integer #(parameter N = 16, M = 4)(in, out);
-	input logic [N-1:0]in;
-	output logic [N-2-M:0]out;
-
-	assign out[N-2-M] = in[N-1];
-	assign out[N-3-M:0] = in[N-3-M:0] << (137 - in[N-2:N-2-M]);
-
-endmodule : FP2Integer
+// module Integer2FP #(parameter N = 16, M = 4)(in, out);
+// // Considering we have a 10 bit mantissa, I assume 11 bit integer input
+// 	input logic [N-2-M:0] in;
+// 	output logic [N-1:0] out;
+//
+// 	logic shift_counter = 0;
+//
+// 	// Saving the sign
+// 	assign out[N-1] = in[N-2-M];
+//
+// 	always_comb
+// 		begin
+// 			// Shifting the absolute value until MSB is 1 and keeping track of the number of shifts
+// 			while (!in[N-3-M])
+// 				begin
+// 					shift_counter = shift_counter + 1;
+// 					in[N-3-M:0] = in[N-3-M:0] << 1;
+// 				end
+// 			// Assigning the mantissa as the shifted absolute value
+// 			// Assigning the exponent as the number of shifts -  a constant 137
+// 			out[N-3-M:0] = in[N-3-M:0];
+// 			out[N-2:N-2-M] = shift_counter - 137;
+// 		end
+// endmodule : Integer2FP
+
+
+
+// module FP2Integer #(parameter N = 16, M = 4)(in, out);
+// 	input logic [N-1:0]in;
+// 	output logic [N-2-M:0]out;
+//
+// 	assign out[N-2-M] = in[N-1];
+// 	assign out[N-3-M:0] = in[N-3-M:0] << (137 - in[N-2:N-2-M]);
+//
+// endmodule : FP2Integer
 
 
 
@@ -199,12 +200,13 @@ module floating_tb;
 	wire flag_double, underflow, zero_flag;
 
 	floating_add adder1(.a(input_a), .b(input_b), .c(result_add), .flag_double(flag_double));
+
 	floating_product multiplier1(.a(input_a), .b(input_b), .c(result_mult), .underflow(underflow), .zero_flag(zero_flag));
 
 
 	reg [15:0] test_mem [29:0][3:0];
 
-	initial $readmemh("../../scripts/fp16_test.hex", test_mem);
+	initial $readmemh("..\..\scripts\fp16_test.hex", test_mem);
 
 
 	initial begin
@@ -212,10 +214,12 @@ module floating_tb;
         static int num_tests = $size(test_mem) * 2;
 
         for (int i=0; i < $size(test_mem); i++) begin
-            input_a = test_mem[i][0];
-            input_b = test_mem[i][1];
+            input_a = 0;
+            input_b = 0;
 
             #10;
+			$display("%d + %d = %d, expected %d", input_a, input_b, result_add, 0);
+			$finish();
             if(result_add != test_mem[i][2]) begin
                 if(num_err < 20)
                     $display("FAIL ADD: %H + %H = %H, expected %H", input_a, input_b, result_add, test_mem[i][2]);
@@ -229,7 +233,6 @@ module floating_tb;
             end
 
         end
-
         $display("Passed %d of %d tests", num_tests-num_err, num_tests);
         $finish();
 	end

src/root.sv

@@ -1,6 +1,7 @@
 // synopsys translate_off
 `timescale 1 ps / 1 ps
 // synopsys translate_on
+`include "FPA_module_test.sv"
 
 module root(
     input  clk,