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+module lead_zeros_enc #(K=10)(in, out);
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+ localparam L = $clog2(K);
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+
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+ input wire [K-1:0] in;
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+ output logic [L-1:0] out;
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+ always_comb begin
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+ casez (in)
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+ 10'b00000_00000 :out = 4'd10;
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+ 10'b00000_0000? :out = 4'd9;
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+ 10'b00000_000?? :out = 4'd8;
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+ 10'b00000_00??? :out = 4'd7;
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+ 10'b00000_0???? :out = 4'd6;
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+ 10'b00000_????? :out = 4'd5;
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+ 10'b0000?_????? :out = 4'd4;
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+ 10'b000??_????? :out = 4'd3;
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+ 10'b00???_????? :out = 4'd2;
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+ 10'b0????_????? :out = 4'd1;
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+ default : out = 4'd0;
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+ endcase
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+ end
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+endmodule : lead_zeros_enc
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+
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+module fp_mult #(parameter N=16, M=5)(input_a, input_b, output_z, clk, reset);
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+ localparam K=N-M-1; // Size of mantissa
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+ localparam L=$clog2(10); // Size of shifting representation
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+
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+ input logic [N-1:0] input_a, input_b;
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+ input logic clk, reset;
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+ output logic [N-1:0] output_z;
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+
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+ // ====================
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+ // Stage 0 store input
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+ // ====================
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+
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+ reg [M-1:0] a_e0, b_e0;
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+ reg [K-1:0] a_m0, b_m0;
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+ reg a_s0, b_s0;
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+
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+ always_ff @(posedge clk) begin
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+ {a_s0, a_e0, a_m0} <= input_a;
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+ {b_s0, b_e0, b_m0} <= input_b;
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+ end
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+
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+ // ====================
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+ // Stage 1 denormalise0
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+ // ====================
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+
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+ reg [M-1:0] a_e1, b_e1;
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+ reg [K-1:0] a_m1, b_m1;
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+ reg z_s1;
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+
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+ // leading zeros
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+ wire [L-1:0] a_z1w, b_z1w;
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+ reg [L-1:0] a_z1, b_z1;
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+
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+ lead_zeros_enc #(.K(K)) lz_a1(a_m1, a_z1w);
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+ lead_zeros_enc #(.K(K)) lz_b1(b_m1, b_z1w);
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+
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+ always_ff @(posedge clk) begin
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+ z_s1 <= a_s0 ^ b_s0; // We don't need to track and propagate signs
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+ {a_e1, a_m1} <= {a_e0, a_m0};
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+ {b_e1, b_m1} <= {b_e0, b_m0};
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+ a_z1 <= a_z1w;
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+ b_z1 <= b_z1w;
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+ end
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+
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+ // ====================
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+ // Stage 2 denormalise1
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+ // ====================
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+
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+ reg [M-1:0] a_e2, b_e2;
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+ reg [K-1:0] a_m2, b_m2;
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+ reg z_s2;
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+
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+ always_ff @(posedge clk) begin
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+ a_e2 <= a_e1 - a_z1;
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+ a_m2 <= a_e1 << a_z1;
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+
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+ b_e2 <= b_e1 - b_z1;
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+ b_m2 <= b_m1 << b_z1;
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+
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+ z_s2 <= z_s1;
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+ end
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+
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+ // ====================
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+ // Stage 3 product
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+ // ====================
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+
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+ reg z_s3;
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+ reg [M-1:0] z_e3;
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+ reg [K*2-1:0] z_p3; // product is double mantissa
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+ wire [K*2-1:0] z_p3w;
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+
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+ assign z_p3w = a_m2 * b_m2;
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+
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+ always_ff @(posedge clk) begin
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+ z_e3 <= a_e2 + b_e2 + 1;
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+ z_p3 <= a_m2 * b_m2;
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+
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+ z_s3 <= z_s2;
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+ end
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+
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+ // ====================
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+ // Stage 4 unpack/normalise0
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+ // ====================
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+
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+ reg z_s4;
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+ reg [M-1:0] z_e4;
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+ reg [K-1:0] z_m4;
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+ reg [1:0] z_bits4; // guard and round_bit
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+ reg z_sticky4;
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+
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+
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+ wire [K-1:0] p3;
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+ // leading zeros
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+ wire [3:0] z_z4w;
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+ reg [3:0] z_z4;
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+
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+ assign p3 = z_p3[K*2-1:K];
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+ lead_zeros_enc #(.K(K)) lz_p3(p3, z_z4w);
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+
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+ always_ff @(posedge clk) begin
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+ z_m4 <= p3;
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+ z_bits4 <= z_p3[K:K-2];
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+ z_sticky4 <= z_p3[K-2:0] != 0;
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+ z_z4 <= z_z4w;
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+
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+ z_e4 <= z_e3;
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+ z_s4 <= z_s3;
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+ end
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+
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+ // ====================
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+ // Stage 5 normalise1
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+ // ====================
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+
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+ reg z_s5;
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+ reg [M-1:0] z_e5;
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+ reg [K-1:0] z_m5;
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+
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+ reg [1:0] z_bits5; // guard and round_bit
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+ reg z_sticky5;
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+
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+ always_ff @(posedge clk) begin
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+ z_e5 <= z_e4 - z_z4;
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+ z_m5 <= z_m4 << z_z4;
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+
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+ case (z_z4)
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+ 4'd0: begin
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+ z_bits5 <= z_bits4;
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+ end
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+ 4'd1: begin
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+ z_m5[0] <= z_bits4[0];
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+ z_bits5 <= {z_bits4[1], 1'b0};
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+ end
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+ 4'd2: begin
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+ z_m5[1-:2] <= z_bits4;
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+ z_bits5 <= 2'b00;
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+ end
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+ default : begin
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+ z_m5[z_z4-1-:2] <= z_bits4;
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+ z_bits5 <= 2'b00;
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+ end
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+ endcase
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+
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+ z_sticky5 <= z_sticky4;
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+ z_s5 <= z_s4;
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+ end
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+
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+ // ====================
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+ // Stage 6 normalise2
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+ // ====================
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+ reg z_s6;
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+ reg [M-1:0] z_e6;
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+ reg [K-1:0] z_m6;
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+
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+ reg [1:0] z_bits6;
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+ reg z_sticky6;
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+
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+
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+ always_ff @(posedge clk) begin
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+ // TODO: Fix this stage
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+ // if ($signed(z_e5) < -126) begin
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+ // shift6 <= $signed(z_e5) -126;
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+ // end else begin
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+ // shift6 <= 0;
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+ // end
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+
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+ z_s6 <= z_s5;
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+ z_e6 <= z_e5;
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+ z_m6 <= z_m5;
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+ z_bits6 <= z_bits5;
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+ z_sticky6 <= z_sticky5;
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+ end
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+
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+ // ====================
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+ // Stage 7 round
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+ // ====================
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+ reg z_s7;
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+ reg [M-1:0] z_e7;
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+ reg [K-1:0] z_m7;
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+
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+ always_ff @(posedge clk) begin
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+ if (z_bits6[0] && (z_bits6[1] | z_sticky6 | z_m6[0])) begin
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+ z_m7 <= z_m6 + 1;
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+ // TODO: Check for all 1s
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+ end else begin
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+ z_m7 <= z_m6;
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+ end
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+ z_e7 <= z_e6;
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+ z_s7 <= z_s6;
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+ end
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+
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+ // ====================
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+ // Stage 8 pack
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+ // ====================
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+ // This stage is skipped as it checks for overflow
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+
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+
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+ always_comb output_z = {z_s7, z_e7, z_m7};
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+
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+endmodule : fp_mult
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