testbench vectors

src/FPA_module_test.sv

@@ -194,22 +194,33 @@ endmodule : FP2Integer
 
 
 module floating_add_tb;
-	logic [15:0] a, b, c;
-	floating_add adder1(a, b, c);
+	reg reset, clk;
+	logic [15:0] input_a, input_b, result_add;
+	wire flag_double;
 
-	task test_inputs;
-		input [15:0] in_a, in_b, expected_c;
-		assign a = in_a;
-		assign b = in_b;
-		#2ps;
-		if(c == expected_c) $display("PASS: a=%b b=%b c=%b", a,b,c);
-		else $error("FAIL: a=%b b=%b c=%b, expected c=%b", a,b,c,expected_c);
-		#2ps;
-	endtask : test_inputs
+	floating_add adder1(.a(input_a), .b(input_b), .c(result_add));
+
+	reg [15:0] test_mem [29:0][3:0];
+
+	initial $readmemh("../../scripts/fp16_test.hex", test_mem);
+
+	// task test_inputs;
+	// 	input [15:0] in_a, in_b, expected_c;
+	// 	assign a = in_a;
+	// 	assign b = in_b;
+	// 	#2ps;
+	// 	if(c == expected_c) $display("PASS: a=%b b=%b c=%b", a,b,c);
+	// 	else $error("FAIL: a=%b b=%b c=%b, expected c=%b", a,b,c,expected_c);
+	// 	#2ps;
+	// endtask : test_inputs
 
 	initial begin
-		test_inputs(16'b0, 16'b0_01111_0000000000, 16'b0_01111_0000000000);
-		$finish();
+		foreach(test_mem[i]) begin
+			input_a = test_mem[i][0];
+			input_b = test_mem[i][1];
+			#10;
+
+		end
 	end
 endmodule : floating_add_tb