Initial

.gitignore

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+/db/
+/incremental_db/
+/output_files/
+/simulation/
+/*_nativelink_simulation.rpt
+/transcript
+/work/
+
+/.idea/
+

Makefile

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+QUARTUS_ROOT := /opt/intelFPGA/20.1
+QUARTUS_DIR = ${QUARTUS_ROOT}/quartus
+MODELSIM_DIR = ${QUARTUS_ROOT}/modelsim_ase
+PROJECT_NAME = altera_devel
+MODELSIM_GUI = ${QUARTUS_DIR}/bin/quartus_sh -t "${QUARTUS_DIR}/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "${PROJECT_NAME}" "${PROJECT_NAME}"
+MODELSIM_BIN = ${MODELSIM_DIR}/bin/vsim
+QUARTUS_MACROS =  --set VERILOG_MACRO="SYNTHESIS=1"
+VSIM_ARGS = -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L work -voptargs="+acc"
+
+tb_file ?=
+tb_dir = $(dirname "${testbench_file}")
+tb_mod ?=
+
+analysis:
+	${QUARTUS_DIR}/bin/quartus_map --read_settings_files=on --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} --analysis_and_elaboration
+
+modelsim: analysis
+	${MODELSIM_GUI}
+
+modelsim_cli:
+	${MODELSIM_BIN} -c
+
+testbench:
+	${MODELSIM_BIN} -c -do "vlog -sv +incdir+${tb_dir} {${tb_file}}; vsim -t 1ps ${VSIM_ARGS} ${tb_mod}; run -all"

altera_devel.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+# Date created = 11:54:18  October 03, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "11:54:18  October 03, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "altera_devel"

altera_devel.qsf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
+# Date created = 11:51:52  October 03, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		altera_devel_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE22F17C6
+set_global_assignment -name TOP_LEVEL_ENTITY root
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:51:52  OCTOBER 03, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name SYSTEMVERILOG_FILE src/root.sv
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

readme.md

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+# Altera Development Repo
+
+### Setup
+Start modelsim GUI
+```bash
+make modelsim
+```
+
+### Running benchmarks
+
+This will run test benchmark in console without opening modelsim GUI
+```bash
+make tb_file=${file} tb_mod=${module} testbench
+# Example
+make tb_file=./src/root.sv tb_mod=root_tb testbench
+```

src/root.sv

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+module root(input a, b, output c);
+	assign c = a & b;
+endmodule : root
+
+
+module root_tb();
+	logic a, b, c;
+	root root_test(
+		.a(a),
+		.b(b),
+		.c(c)
+	);
+
+	task test_inputs;
+		input in_a, in_b, expected_c;
+		a = in_a;
+		b = in_b;
+		#2ps;
+		if(c == expected_c) $display("PASS: a=%b b=%b c=%b", a,b,c);
+		else $error("FAIL: a=%b b=%b c=%b, expected c=%b", a,b,c,expected_c);
+		#2ps;
+	endtask : test_inputs
+
+	initial begin
+		test_inputs(0, 0, 0);
+		test_inputs(0, 1, 0);
+		test_inputs(1, 0, 0);
+		test_inputs(1, 1, 1);
+		test_inputs(1, 1, 0);
+		$finish();
+	end
+
+endmodule : root_tb