fpa16

src/FPA_module_test.sv

@@ -150,41 +150,24 @@ endmodule : floating_product
 
 
 
-// module Integer2FP #(parameter N = 16, M = 4)(in, out);
-// // Considering we have a 10 bit mantissa, I assume 11 bit integer input
-// 	input logic [N-2-M:0] in;
-// 	output logic [N-1:0] out;
-//
-// 	logic shift_counter = 0;
-//
-// 	// Saving the sign
-// 	assign out[N-1] = in[N-2-M];
-//
-// 	always_comb
-// 		begin
-// 			// Shifting the absolute value until MSB is 1 and keeping track of the number of shifts
-// 			while (!in[N-3-M])
-// 				begin
-// 					shift_counter = shift_counter + 1;
-// 					in[N-3-M:0] = in[N-3-M:0] << 1;
-// 				end
-// 			// Assigning the mantissa as the shifted absolute value
-// 			// Assigning the exponent as the number of shifts -  a constant 137
-// 			out[N-3-M:0] = in[N-3-M:0];
-// 			out[N-2:N-2-M] = shift_counter - 137;
-// 		end
-// endmodule : Integer2FP
-
-
-
-// module FP2Integer #(parameter N = 16, M = 4)(in, out);
-// 	input logic [N-1:0]in;
-// 	output logic [N-2-M:0]out;
-//
-// 	assign out[N-2-M] = in[N-1];
-// 	assign out[N-3-M:0] = in[N-3-M:0] << (137 - in[N-2:N-2-M]);
-//
-// endmodule : FP2Integer
+module pipe #(parameter N=16)pipe(clk, reset, Q, D);
+	input logic clk, reset;
+	input logic [N-1:0] D;
+	output reg [N-1:0] Q;
+	reg [N-1:0] in_pipe;
+	
+	always @(posedge clk or negedge reset)
+		begin
+			if(reset) in_pipe = 0;
+			else in_pipe = D;
+		end
+	
+	always @(posedge clk or negedge reset)
+		begin
+			if(reset) Q = 0;
+			else Q = in_pipe;
+		end
+endmodule : pipe